uint32_t *kernel_out, void *prog_data_out)
{
struct brw_context *brw = blorp->driver_ctx;
- return brw_search_cache(&brw->cache, BRW_CACHE_BLORP_PROG,
- key, key_size, kernel_out, prog_data_out);
+ return brw_search_cache(&brw->cache, BRW_CACHE_BLORP_PROG, key, key_size,
+ kernel_out, prog_data_out, true);
}
static bool
brw->blorp.exec = gen5_blorp_exec;
break;
case 6:
- brw->blorp.mocs.tex = 0;
- brw->blorp.mocs.rb = 0;
- brw->blorp.mocs.vb = 0;
brw->blorp.exec = gen6_blorp_exec;
break;
case 7:
- brw->blorp.mocs.tex = GEN7_MOCS_L3;
- brw->blorp.mocs.rb = GEN7_MOCS_L3;
- brw->blorp.mocs.vb = GEN7_MOCS_L3;
if (devinfo->is_haswell) {
brw->blorp.exec = gen75_blorp_exec;
} else {
}
break;
case 8:
- brw->blorp.mocs.tex = BDW_MOCS_WB;
- brw->blorp.mocs.rb = BDW_MOCS_PTE;
- brw->blorp.mocs.vb = BDW_MOCS_WB;
brw->blorp.exec = gen8_blorp_exec;
break;
case 9:
- brw->blorp.mocs.tex = SKL_MOCS_WB;
- brw->blorp.mocs.rb = SKL_MOCS_PTE;
- brw->blorp.mocs.vb = SKL_MOCS_WB;
brw->blorp.exec = gen9_blorp_exec;
break;
case 10:
- brw->blorp.mocs.tex = CNL_MOCS_WB;
- brw->blorp.mocs.rb = CNL_MOCS_PTE;
- brw->blorp.mocs.vb = CNL_MOCS_WB;
brw->blorp.exec = gen10_blorp_exec;
break;
+ case 11:
+ brw->blorp.exec = gen11_blorp_exec;
+ break;
+
default:
unreachable("Invalid gen");
}
static void
blorp_surf_for_miptree(struct brw_context *brw,
struct blorp_surf *surf,
- struct intel_mipmap_tree *mt,
+ const struct intel_mipmap_tree *mt,
enum isl_aux_usage aux_usage,
bool is_render_target,
unsigned *level,
intel_miptree_check_level_layer(mt, *level, start_layer + i);
}
- surf->surf = &mt->surf;
- surf->addr = (struct blorp_address) {
- .buffer = mt->bo,
- .offset = mt->offset,
- .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
+ *surf = (struct blorp_surf) {
+ .surf = &mt->surf,
+ .addr = (struct blorp_address) {
+ .buffer = mt->bo,
+ .offset = mt->offset,
+ .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
+ .mocs = brw_get_bo_mocs(devinfo, mt->bo),
+ },
+ .aux_usage = aux_usage,
+ .tile_x_sa = mt->level[*level].level_x,
+ .tile_y_sa = mt->level[*level].level_y,
};
- surf->aux_usage = aux_usage;
-
- struct isl_surf *aux_surf = NULL;
- if (mt->mcs_buf)
- aux_surf = &mt->mcs_buf->surf;
- else if (mt->hiz_buf)
- aux_surf = &mt->hiz_buf->surf;
-
- if (mt->format == MESA_FORMAT_S_UINT8 && is_render_target &&
- devinfo->gen <= 7)
- mt->r8stencil_needs_update = true;
-
if (surf->aux_usage == ISL_AUX_USAGE_HIZ &&
!intel_miptree_level_has_hiz(mt, *level))
surf->aux_usage = ISL_AUX_USAGE_NONE;
/* We only really need a clear color if we also have an auxiliary
* surface. Without one, it does nothing.
*/
- surf->clear_color = mt->fast_clear_color;
+ surf->clear_color =
+ intel_miptree_get_clear_color(devinfo, mt, mt->surf.format,
+ !is_render_target, (struct brw_bo **)
+ &surf->clear_color_addr.buffer,
+ &surf->clear_color_addr.offset);
- surf->aux_surf = aux_surf;
+ surf->aux_surf = &mt->aux_buf->surf;
surf->aux_addr = (struct blorp_address) {
.reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
+ .mocs = surf->addr.mocs,
};
- if (mt->mcs_buf) {
- surf->aux_addr.buffer = mt->mcs_buf->bo;
- surf->aux_addr.offset = mt->mcs_buf->offset;
- } else {
- assert(mt->hiz_buf);
- assert(surf->aux_usage == ISL_AUX_USAGE_HIZ);
-
- surf->aux_addr.buffer = mt->hiz_buf->bo;
- surf->aux_addr.offset = mt->hiz_buf->offset;
- }
+ surf->aux_addr.buffer = mt->aux_buf->bo;
+ surf->aux_addr.offset = mt->aux_buf->offset;
} else {
surf->aux_addr = (struct blorp_address) {
.buffer = NULL,
*level -= mt->first_level;
}
+static bool
+brw_blorp_supports_dst_format(struct brw_context *brw, mesa_format format)
+{
+ /* If it's renderable, it's definitely supported. */
+ if (brw->mesa_format_supports_render[format])
+ return true;
+
+ /* BLORP can't compress anything */
+ if (_mesa_is_format_compressed(format))
+ return false;
+
+ /* No exotic formats such as GL_LUMINANCE_ALPHA */
+ if (_mesa_get_format_bits(format, GL_RED_BITS) == 0 &&
+ _mesa_get_format_bits(format, GL_DEPTH_BITS) == 0 &&
+ _mesa_get_format_bits(format, GL_STENCIL_BITS) == 0)
+ return false;
+
+ return true;
+}
+
static enum isl_format
brw_blorp_to_isl_format(struct brw_context *brw, mesa_format format,
bool is_render_target)
return ISL_FORMAT_R32_FLOAT;
case MESA_FORMAT_Z_UNORM16:
return ISL_FORMAT_R16_UNORM;
- default: {
+ default:
if (is_render_target) {
- assert(brw->mesa_format_supports_render[format]);
- return brw->mesa_to_isl_render_format[format];
+ assert(brw_blorp_supports_dst_format(brw, format));
+ if (brw->mesa_format_supports_render[format]) {
+ return brw->mesa_to_isl_render_format[format];
+ } else {
+ return brw_isl_format_for_mesa_format(format);
+ }
} else {
+ /* Some destinations (is_render_target == true) are supported by
+ * blorp even though we technically can't render to them.
+ */
return brw_isl_format_for_mesa_format(format);
}
- break;
- }
}
}
float src_x1, float src_y1,
float dst_x0, float dst_y0,
float dst_x1, float dst_y1,
- GLenum filter, bool mirror_x, bool mirror_y,
+ GLenum gl_filter, bool mirror_x, bool mirror_y,
bool decode_srgb, bool encode_srgb)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
- DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
+ DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f) "
"to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
__func__,
src_mt->surf.samples, _mesa_get_format_name(src_mt->format), src_mt,
src_format = dst_format = MESA_FORMAT_R_FLOAT32;
}
- enum isl_format src_isl_format = brw_isl_format_for_mesa_format(src_format);
+ enum blorp_filter blorp_filter;
+ if (fabsf(dst_x1 - dst_x0) == fabsf(src_x1 - src_x0) &&
+ fabsf(dst_y1 - dst_y0) == fabsf(src_y1 - src_y0)) {
+ if (src_mt->surf.samples > 1 && dst_mt->surf.samples <= 1) {
+ /* From the OpenGL ES 3.2 specification, section 16.2.1:
+ *
+ * "If the read framebuffer is multisampled (its effective value
+ * of SAMPLE_BUFFERS is one) and the draw framebuffer is not (its
+ * value of SAMPLE_BUFFERS is zero), the samples corresponding to
+ * each pixel location in the source are converted to a single
+ * sample before being written to the destination. The filter
+ * parameter is ignored. If the source formats are integer types
+ * or stencil values, a single sample’s value is selected for each
+ * pixel. If the source formats are floating-point or normalized
+ * types, the sample values for each pixel are resolved in an
+ * implementation-dependent manner. If the source formats are
+ * depth values, sample values are resolved in an implementation-
+ * dependent manner where the result will be between the minimum
+ * and maximum depth values in the pixel."
+ *
+ * For depth and stencil resolves, we choose to always use the value
+ * at sample 0.
+ */
+ GLenum base_format = _mesa_get_format_base_format(src_mt->format);
+ if (base_format == GL_DEPTH_COMPONENT ||
+ base_format == GL_STENCIL_INDEX ||
+ base_format == GL_DEPTH_STENCIL ||
+ _mesa_is_format_integer(src_mt->format)) {
+ /* The OpenGL ES 3.2 spec says:
+ *
+ * "If the source formats are integer types or stencil values,
+ * a single sample's value is selected for each pixel."
+ *
+ * Just take sample 0 in this case.
+ */
+ blorp_filter = BLORP_FILTER_SAMPLE_0;
+ } else {
+ blorp_filter = BLORP_FILTER_AVERAGE;
+ }
+ } else {
+ /* From the OpenGL 4.6 specification, section 18.3.1:
+ *
+ * "If the source and destination dimensions are identical, no
+ * filtering is applied."
+ *
+ * Using BLORP_FILTER_NONE will also handle the upsample case by
+ * replicating the one value in the source to all values in the
+ * destination.
+ */
+ blorp_filter = BLORP_FILTER_NONE;
+ }
+ } else if (gl_filter == GL_LINEAR ||
+ gl_filter == GL_SCALED_RESOLVE_FASTEST_EXT ||
+ gl_filter == GL_SCALED_RESOLVE_NICEST_EXT) {
+ blorp_filter = BLORP_FILTER_BILINEAR;
+ } else {
+ blorp_filter = BLORP_FILTER_NEAREST;
+ }
+
+ enum isl_format src_isl_format =
+ brw_blorp_to_isl_format(brw, src_format, false);
enum isl_aux_usage src_aux_usage =
intel_miptree_texture_aux_usage(brw, src_mt, src_isl_format);
/* We do format workarounds for some depth formats so we can't reliably
intel_miptree_prepare_access(brw, src_mt, src_level, 1, src_layer, 1,
src_aux_usage, src_clear_supported);
+ enum isl_format dst_isl_format =
+ brw_blorp_to_isl_format(brw, dst_format, true);
enum isl_aux_usage dst_aux_usage =
- intel_miptree_render_aux_usage(brw, dst_mt, encode_srgb, false);
+ intel_miptree_render_aux_usage(brw, dst_mt, dst_isl_format,
+ false, false);
const bool dst_clear_supported = dst_aux_usage != ISL_AUX_USAGE_NONE;
intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
dst_aux_usage, dst_clear_supported);
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_blit(&batch, &src_surf, src_level, src_layer,
- brw_blorp_to_isl_format(brw, src_format, false), src_isl_swizzle,
+ src_isl_format, src_isl_swizzle,
&dst_surf, dst_level, dst_layer,
- brw_blorp_to_isl_format(brw, dst_format, true),
- ISL_SWIZZLE_IDENTITY,
+ dst_isl_format, ISL_SWIZZLE_IDENTITY,
src_x0, src_y0, src_x1, src_y1,
dst_x0, dst_y0, dst_x1, dst_y1,
- filter, mirror_x, mirror_y);
+ blorp_filter, mirror_x, mirror_y);
blorp_batch_finish(&batch);
intel_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
blorp_surf_for_miptree(brw, &dst_surf, dst_mt, dst_aux_usage, true,
&dst_level, dst_layer, 1, &tmp_surfs[1]);
+ /* The hardware seems to have issues with having a two different format
+ * views of the same texture in the sampler cache at the same time. It's
+ * unclear exactly what the issue is but it hurts glCopyImageSubData
+ * particularly badly because it does a lot of format reinterprets. We
+ * badly need better understanding of the issue and a better fix but this
+ * works for now and fixes CTS tests.
+ *
+ * TODO: Remove this hack!
+ */
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
+
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw, 0);
blorp_copy(&batch, &src_surf, src_level, src_layer,
src_x, src_y, dst_x, dst_y, src_width, src_height);
blorp_batch_finish(&batch);
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
+
intel_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
dst_aux_usage);
}
src_mt = find_miptree(buffer_bit, src_irb);
dst_mt = find_miptree(buffer_bit, dst_irb);
- /* We can't handle format conversions between Z24 and other formats
- * since we have to lie about the surface format. See the comments in
- * brw_blorp_surface_info::set().
- */
- if ((src_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT) !=
- (dst_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT))
- return false;
-
/* We also can't handle any combined depth-stencil formats because we
* have to reinterpret as a color format.
*/
struct intel_mipmap_tree *src_mt = src_irb->mt;
struct intel_mipmap_tree *dst_mt = intel_image->mt;
- /* There is support for only up to eight samples. */
- if (src_mt->surf.samples > 8 || dst_mt->surf.samples > 8)
- return false;
-
- if (_mesa_get_format_base_format(src_rb->Format) !=
- _mesa_get_format_base_format(dst_image->TexFormat)) {
- return false;
- }
-
- /* We can't handle format conversions between Z24 and other formats since
- * we have to lie about the surface format. See the comments in
- * brw_blorp_surface_info::set().
- */
- if ((src_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT) !=
- (dst_mt->format == MESA_FORMAT_Z24_UNORM_X8_UINT)) {
- return false;
- }
-
- /* We also can't handle any combined depth-stencil formats because we
- * have to reinterpret as a color format.
+ /* We can't handle any combined depth-stencil formats because we have to
+ * reinterpret as a color format.
*/
if (_mesa_get_format_base_format(src_mt->format) == GL_DEPTH_STENCIL ||
_mesa_get_format_base_format(dst_mt->format) == GL_DEPTH_STENCIL)
return false;
- if (!brw->mesa_format_supports_render[dst_image->TexFormat])
+ if (!brw_blorp_supports_dst_format(brw, dst_image->TexFormat))
return false;
/* Source clipping shouldn't be necessary, since copytexsubimage (in
* data which we need to copy into a BO.
*/
struct brw_bo *bo =
- brw_bo_alloc(brw->bufmgr, "tmp_tex_subimage_src", size, 64);
+ brw_bo_alloc(brw->bufmgr, "tmp_tex_subimage_src", size,
+ BRW_MEMZONE_OTHER);
if (bo == NULL) {
perf_debug("intel_texsubimage: temp bo creation failed: size = %u\n",
size);
brw, src_bo, src_format,
src_offset + i * src_image_stride,
width, height, 1,
- src_row_stride, 0);
+ src_row_stride,
+ ISL_TILING_LINEAR, 0);
if (!src_mt) {
perf_debug("intel_texsubimage: miptree creation for src failed\n");
brw, dst_bo, dst_format,
dst_offset + i * dst_image_stride,
width, height, 1,
- dst_row_stride, 0);
+ dst_row_stride,
+ ISL_TILING_LINEAR, 0);
if (!dst_mt) {
perf_debug("intel_texsubimage: miptree creation for src failed\n");
result = true;
+ /* As we implement PBO transfers by binding the user-provided BO as a
+ * fake framebuffer and rendering to it. This breaks the invariant of the
+ * GL that nothing is able to render to a BO, causing nondeterministic
+ * corruption issues because the render cache is not coherent with a
+ * number of other caches that the BO could potentially be bound to
+ * afterwards.
+ *
+ * This could be solved in the same way that we guarantee texture
+ * coherency after a texture is attached to a framebuffer and
+ * rendered to, but that would involve checking *all* BOs bound to
+ * the pipeline for the case we need to emit a cache flush due to
+ * previous rendering to any of them -- Including vertex, index,
+ * uniform, atomic counter, shader image, transform feedback,
+ * indirect draw buffers, etc.
+ *
+ * That would increase the per-draw call overhead even though it's
+ * very unlikely that any of the BOs bound to the pipeline has been
+ * rendered to via a PBO at any point, so it seems better to just
+ * flush here unconditionally.
+ */
+ brw_emit_mi_flush(brw);
+
err:
brw_bo_unreference(dst_bo);
static bool
set_write_disables(const struct intel_renderbuffer *irb,
- const GLubyte *color_mask, bool *color_write_disable)
+ const unsigned color_mask, bool *color_write_disable)
{
/* Format information in the renderbuffer represents the requirements
* given by the client. There are cases where the backing miptree uses,
assert(components > 0);
for (int i = 0; i < components; i++) {
- color_write_disable[i] = !color_mask[i];
- disables = disables || !color_mask[i];
+ color_write_disable[i] = !(color_mask & (1 << i));
+ disables = disables || color_write_disable[i];
}
return disables;
mesa_format format = irb->Base.Base.Format;
if (!encode_srgb && _mesa_get_format_color_encoding(format) == GL_SRGB)
format = _mesa_get_srgb_format_linear(format);
+ enum isl_format isl_format = brw->mesa_to_isl_render_format[format];
x0 = fb->_Xmin;
x1 = fb->_Xmax;
bool can_fast_clear = !partial_clear;
bool color_write_disable[4] = { false, false, false, false };
- if (set_write_disables(irb, ctx->Color.ColorMask[buf], color_write_disable))
+ if (set_write_disables(irb, GET_COLORMASK(ctx->Color.ColorMask, buf),
+ color_write_disable))
can_fast_clear = false;
/* We store clear colors as floats or uints as needed. If there are
/* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
*/
- if (can_fast_clear && !irb->mt->mcs_buf) {
+ if (can_fast_clear && !irb->mt->aux_buf) {
assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
- if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
- /* There are a few reasons in addition to out-of-memory, that can
- * cause intel_miptree_alloc_non_msrt_mcs to fail. Try to recover by
- * falling back to non-fast clear.
- */
+ if (!intel_miptree_alloc_aux(brw, irb->mt)) {
+ /* We're out of memory. Fall back to a non-fast clear. */
can_fast_clear = false;
}
}
+ /* FINISHME: Debug and enable fast clears */
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ if (devinfo->gen >= 11)
+ can_fast_clear = false;
+
if (can_fast_clear) {
const enum isl_aux_state aux_state =
intel_miptree_get_aux_state(irb->mt, irb->mt_level, irb->mt_layer);
brw_meta_convert_fast_clear_color(brw, irb->mt,
&ctx->Color.ClearColor);
- bool same_clear_color =
- !intel_miptree_set_clear_color(ctx, irb->mt, clear_color);
+ intel_miptree_set_clear_color(brw, irb->mt, clear_color);
- /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
+ /* If the buffer is already in ISL_AUX_STATE_CLEAR, the clear
* is redundant and can be skipped.
*/
- if (aux_state == ISL_AUX_STATE_CLEAR && same_clear_color)
+ if (aux_state == ISL_AUX_STATE_CLEAR)
return;
DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__,
brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH);
struct blorp_batch batch;
- blorp_batch_init(&brw->blorp, &batch, brw, 0);
- blorp_fast_clear(&batch, &surf,
- brw->mesa_to_isl_render_format[format],
+ blorp_batch_init(&brw->blorp, &batch, brw,
+ BLORP_BATCH_NO_UPDATE_CLEAR_COLOR);
+ blorp_fast_clear(&batch, &surf, isl_format,
level, irb->mt_layer, num_layers,
x0, y0, x1, y1);
blorp_batch_finish(&batch);
irb->mt, irb->mt_level, irb->mt_layer, num_layers);
enum isl_aux_usage aux_usage =
- intel_miptree_render_aux_usage(brw, irb->mt, encode_srgb, false);
+ intel_miptree_render_aux_usage(brw, irb->mt, isl_format,
+ false, false);
intel_miptree_prepare_render(brw, irb->mt, level, irb->mt_layer,
- num_layers, encode_srgb, false);
+ num_layers, aux_usage);
struct isl_surf isl_tmp[2];
struct blorp_surf surf;
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw, 0);
- blorp_clear(&batch, &surf,
- brw->mesa_to_isl_render_format[format],
- ISL_SWIZZLE_IDENTITY,
+ blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
level, irb->mt_layer, num_layers,
x0, y0, x1, y1,
clear_color, color_write_disable);
blorp_batch_finish(&batch);
intel_miptree_finish_render(brw, irb->mt, level, irb->mt_layer,
- num_layers, encode_srgb, false);
+ num_layers, aux_usage);
}
return;
assert(level == irb->mt_level);
assert(start_layer == irb->mt_layer);
assert(num_layers == fb->MaxNumLayers ? irb->layer_count : 1);
- } else {
- level = irb->mt_level;
- start_layer = irb->mt_layer;
- num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
}
+ level = irb->mt_level;
+ start_layer = irb->mt_layer;
+ num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
+
stencil_mask = ctx->Stencil.WriteMask[0] & 0xff;
intel_miptree_prepare_access(brw, stencil_mt, level, 1,
void
brw_blorp_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt,
unsigned level, unsigned layer,
- enum blorp_fast_clear_op resolve_op)
+ enum isl_aux_op resolve_op)
{
DBG("%s to mt %p level %u layer %u\n", __FUNCTION__, mt, level, layer);
struct blorp_batch batch;
blorp_batch_init(&brw->blorp, &batch, brw, 0);
- blorp_ccs_resolve(&batch, &surf, level, layer,
+ blorp_ccs_resolve(&batch, &surf, level, layer, 1,
brw_blorp_to_isl_format(brw, format, true),
resolve_op);
blorp_batch_finish(&batch);
void
intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
unsigned int level, unsigned int start_layer,
- unsigned int num_layers, enum blorp_hiz_op op)
+ unsigned int num_layers, enum isl_aux_op op)
{
assert(intel_miptree_level_has_hiz(mt, level));
- assert(op != BLORP_HIZ_OP_NONE);
+ assert(op != ISL_AUX_OP_NONE);
const struct gen_device_info *devinfo = &brw->screen->devinfo;
const char *opname = NULL;
switch (op) {
- case BLORP_HIZ_OP_DEPTH_RESOLVE:
+ case ISL_AUX_OP_FULL_RESOLVE:
opname = "depth resolve";
break;
- case BLORP_HIZ_OP_HIZ_RESOLVE:
+ case ISL_AUX_OP_AMBIGUATE:
opname = "hiz ambiguate";
break;
- case BLORP_HIZ_OP_DEPTH_CLEAR:
+ case ISL_AUX_OP_FAST_CLEAR:
opname = "depth clear";
break;
- case BLORP_HIZ_OP_NONE:
- opname = "noop?";
- break;
+ case ISL_AUX_OP_PARTIAL_RESOLVE:
+ case ISL_AUX_OP_NONE:
+ unreachable("Invalid HiZ op");
}
DBG("%s %s to mt %p level %d layers %d-%d\n",
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
}
- assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->hiz_buf);
+ assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->aux_buf);
struct isl_surf isl_tmp[2];
struct blorp_surf surf;
&level, start_layer, num_layers, isl_tmp);
struct blorp_batch batch;
- blorp_batch_init(&brw->blorp, &batch, brw, 0);
+ blorp_batch_init(&brw->blorp, &batch, brw,
+ BLORP_BATCH_NO_UPDATE_CLEAR_COLOR);
blorp_hiz_op(&batch, &surf, level, start_layer, num_layers, op);
blorp_batch_finish(&batch);
projects / mesa.git / blobdiff