i965/blorp: Add support for source swizzle

[mesa.git] / src / mesa / drivers / dri / i965 / brw_blorp.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 131e1558f38e66ee981663482eb04c65d980b899..04a019e07178bf46da0e763fb75ffdc00370ea7f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -26,10 +26,7 @@
 #include "intel_fbo.h"
 
 #include "brw_blorp.h"
-#include "brw_defines.h"
 #include "brw_state.h"
-#include "gen6_blorp.h"
-#include "gen7_blorp.h"
 
 #define FILE_DEBUG_FLAG DEBUG_BLORP
 
@@ -46,7 +43,8 @@ brw_blorp_mip_info::brw_blorp_mip_info()
 
 brw_blorp_surface_info::brw_blorp_surface_info()
    : map_stencil_as_y_tiled(false),
-     num_samples(0)
+     num_samples(0),
+     swizzle(SWIZZLE_XYZW)
 {
 }
 
@@ -118,12 +116,11 @@ brw_blorp_surface_info::set(struct brw_context *brw,
       this->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
       break;
    default: {
-      mesa_format linear_format = _mesa_get_srgb_format_linear(format);
       if (is_render_target) {
-         assert(brw->format_supported_as_render_target[linear_format]);
-         this->brw_surfaceformat = brw->render_target_format[linear_format];
+         assert(brw->format_supported_as_render_target[format]);
+         this->brw_surfaceformat = brw->render_target_format[format];
       } else {
-         this->brw_surfaceformat = brw_format_for_mesa_format(linear_format);
+         this->brw_surfaceformat = brw_format_for_mesa_format(format);
       }
       break;
    }
@@ -144,7 +141,9 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
 {
    uint32_t mask_x, mask_y;
 
-   intel_miptree_get_tile_masks(mt, &mask_x, &mask_y, map_stencil_as_y_tiled);
+   intel_get_tile_masks(mt->tiling, mt->tr_mode, mt->cpp,
+                        map_stencil_as_y_tiled,
+                        &mask_x, &mask_y);
 
    *tile_x = x_offset & mask_x;
    *tile_y = y_offset & mask_y;
@@ -155,20 +154,20 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
 }
 
 
-brw_blorp_params::brw_blorp_params()
+brw_blorp_params::brw_blorp_params(unsigned num_varyings,
+                                   unsigned num_draw_buffers,
+                                   unsigned num_layers)
    : x0(0),
      y0(0),
      x1(0),
      y1(0),
      depth_format(0),
      hiz_op(GEN6_HIZ_OP_NONE),
-     fast_clear_op(GEN7_FAST_CLEAR_OP_NONE),
-     use_wm_prog(false)
+     use_wm_prog(false),
+     num_varyings(num_varyings),
+     num_draw_buffers(num_draw_buffers),
+     num_layers(num_layers)
 {
-   color_write_disable[0] = false;
-   color_write_disable[1] = false;
-   color_write_disable[2] = false;
-   color_write_disable[3] = false;
 }
 
 extern "C" {
@@ -220,13 +219,13 @@ brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
     * data with different formats, which blorp does for stencil and depth
     * data.
     */
-   intel_batchbuffer_emit_mi_flush(brw);
+   brw_emit_mi_flush(brw);
 
 retry:
    intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING);
    intel_batchbuffer_save_state(brw);
    drm_intel_bo *saved_bo = brw->batch.bo;
-   uint32_t saved_used = brw->batch.used;
+   uint32_t saved_used = USED_BATCH(brw->batch);
    uint32_t saved_state_batch_offset = brw->batch.state_batch_offset;
 
    switch (brw->gen) {
@@ -245,7 +244,7 @@ retry:
     * reserved enough space that a wrap will never happen.
     */
    assert(brw->batch.bo == saved_bo);
-   assert((brw->batch.used - saved_used) * 4 +
+   assert((USED_BATCH(brw->batch) - saved_used) * 4 +
           (saved_state_batch_offset - brw->batch.state_batch_offset) <
           estimated_max_batch_usage);
    /* Shut up compiler warnings on release build */
@@ -283,7 +282,7 @@ retry:
    /* Flush the sampler cache so any texturing from the destination is
     * coherent.
     */
-   intel_batchbuffer_emit_mi_flush(brw);
+   brw_emit_mi_flush(brw);
 }
 
 brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
@@ -320,8 +319,14 @@ brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
     * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
     * prevents the clobbering.
     */
-   depth.width = ALIGN(depth.width, 8);
-   depth.height = ALIGN(depth.height, 4);
+   dst.num_samples = mt->num_samples;
+   if (dst.num_samples > 1) {
+      depth.width = ALIGN(mt->logical_width0, 8);
+      depth.height = ALIGN(mt->logical_height0, 4);
+   } else {
+      depth.width = ALIGN(depth.width, 8);
+      depth.height = ALIGN(depth.height, 4);
+   }
 
    x1 = depth.width;
    y1 = depth.height;