#include "intel_fbo.h"
#include "brw_blorp.h"
-#include "brw_defines.h"
#include "brw_state.h"
-#include "gen6_blorp.h"
-#include "gen7_blorp.h"
#define FILE_DEBUG_FLAG DEBUG_BLORP
brw_blorp_surface_info::brw_blorp_surface_info()
: map_stencil_as_y_tiled(false),
- num_samples(0)
+ num_samples(0),
+ swizzle(SWIZZLE_XYZW)
{
}
brw_blorp_surface_info::set(struct brw_context *brw,
struct intel_mipmap_tree *mt,
unsigned int level, unsigned int layer,
- bool is_render_target)
+ mesa_format format, bool is_render_target)
{
brw_blorp_mip_info::set(mt, level, layer);
this->num_samples = mt->num_samples;
- this->array_spacing_lod0 = mt->array_spacing_lod0;
+ this->array_layout = mt->array_layout;
this->map_stencil_as_y_tiled = false;
this->msaa_layout = mt->msaa_layout;
- switch (mt->format) {
+ if (format == MESA_FORMAT_NONE)
+ format = mt->format;
+
+ switch (format) {
case MESA_FORMAT_S_UINT8:
/* The miptree is a W-tiled stencil buffer. Surface states can't be set
* up for W tiling, so we'll need to use Y tiling and have the WM
this->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
break;
default: {
- mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
if (is_render_target) {
- assert(brw->format_supported_as_render_target[linear_format]);
- this->brw_surfaceformat = brw->render_target_format[linear_format];
+ assert(brw->format_supported_as_render_target[format]);
+ this->brw_surfaceformat = brw->render_target_format[format];
} else {
- this->brw_surfaceformat = brw_format_for_mesa_format(linear_format);
+ this->brw_surfaceformat = brw_format_for_mesa_format(format);
}
break;
}
brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
uint32_t *tile_y) const
{
- struct intel_region *region = mt->region;
uint32_t mask_x, mask_y;
- intel_region_get_tile_masks(region, &mask_x, &mask_y,
- map_stencil_as_y_tiled);
+ intel_get_tile_masks(mt->tiling, mt->tr_mode, mt->cpp,
+ map_stencil_as_y_tiled,
+ &mask_x, &mask_y);
*tile_x = x_offset & mask_x;
*tile_y = y_offset & mask_y;
- return intel_region_get_aligned_offset(region, x_offset & ~mask_x,
- y_offset & ~mask_y,
- map_stencil_as_y_tiled);
+ return intel_miptree_get_aligned_offset(mt, x_offset & ~mask_x,
+ y_offset & ~mask_y,
+ map_stencil_as_y_tiled);
}
-brw_blorp_params::brw_blorp_params()
+brw_blorp_params::brw_blorp_params(unsigned num_varyings,
+ unsigned num_draw_buffers,
+ unsigned num_layers)
: x0(0),
y0(0),
x1(0),
y1(0),
depth_format(0),
hiz_op(GEN6_HIZ_OP_NONE),
- fast_clear_op(GEN7_FAST_CLEAR_OP_NONE),
- use_wm_prog(false)
+ use_wm_prog(false),
+ num_varyings(num_varyings),
+ num_draw_buffers(num_draw_buffers),
+ num_layers(num_layers)
{
- color_write_disable[0] = false;
- color_write_disable[1] = false;
- color_write_disable[2] = false;
- color_write_disable[3] = false;
}
extern "C" {
}
DBG("%s %s to mt %p level %d layer %d\n",
- __FUNCTION__, opname, mt, level, layer);
+ __func__, opname, mt, level, layer);
if (brw->gen >= 8) {
gen8_hiz_exec(brw, mt, level, layer, op);
* data with different formats, which blorp does for stencil and depth
* data.
*/
- intel_batchbuffer_emit_mi_flush(brw);
+ brw_emit_mi_flush(brw);
retry:
intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING);
intel_batchbuffer_save_state(brw);
drm_intel_bo *saved_bo = brw->batch.bo;
- uint32_t saved_used = brw->batch.used;
+ uint32_t saved_used = USED_BATCH(brw->batch);
uint32_t saved_state_batch_offset = brw->batch.state_batch_offset;
switch (brw->gen) {
break;
default:
/* BLORP is not supported before Gen6. */
- assert(false);
- break;
+ unreachable("not reached");
}
/* Make sure we didn't wrap the batch unintentionally, and make sure we
* reserved enough space that a wrap will never happen.
*/
assert(brw->batch.bo == saved_bo);
- assert((brw->batch.used - saved_used) * 4 +
+ assert((USED_BATCH(brw->batch) - saved_used) * 4 +
(saved_state_batch_offset - brw->batch.state_batch_offset) <
estimated_max_batch_usage);
/* Shut up compiler warnings on release build */
/* We've smashed all state compared to what the normal 3D pipeline
* rendering tracks for GL.
*/
- brw->state.dirty.brw = ~0;
- brw->state.dirty.cache = ~0;
+ brw->ctx.NewDriverState = ~0ull;
+ brw->no_depth_or_stencil = false;
brw->ib.type = -1;
- intel_batchbuffer_clear_cache(brw);
/* Flush the sampler cache so any texturing from the destination is
* coherent.
*/
- intel_batchbuffer_emit_mi_flush(brw);
+ brw_emit_mi_flush(brw);
}
brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
* not 8. But commit 1f112cc increased the alignment from 4 to 8, which
* prevents the clobbering.
*/
- depth.width = ALIGN(depth.width, 8);
- depth.height = ALIGN(depth.height, 4);
+ dst.num_samples = mt->num_samples;
+ if (dst.num_samples > 1) {
+ depth.width = ALIGN(mt->logical_width0, 8);
+ depth.height = ALIGN(mt->logical_height0, 4);
+ } else {
+ depth.width = ALIGN(depth.width, 8);
+ depth.height = ALIGN(depth.height, 4);
+ }
x1 = depth.width;
y1 = depth.height;
- assert(intel_miptree_slice_has_hiz(mt, level, layer));
+ assert(intel_miptree_level_has_hiz(mt, level));
switch (mt->format) {
case MESA_FORMAT_Z_UNORM16: depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;
case MESA_FORMAT_Z_FLOAT32: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
case MESA_FORMAT_Z24_UNORM_X8_UINT: depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
- default: assert(0); break;
+ default: unreachable("not reached");
}
}
projects / mesa.git / blobdiff