i965/vec4: Make with_writemask() non-static.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_blorp.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 65c99523700d60001ad2daa8678d3965d36efe1f..1576ff2a3842c55ab12ab20b5bd4cc353b2d87d2 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -191,9 +191,7 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 void
 brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
 {
-   struct intel_context *intel = &brw->intel;
-
-   switch (intel->gen) {
+   switch (brw->gen) {
    case 6:
       gen6_blorp_exec(brw, params);
       break;
@@ -206,7 +204,7 @@ brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
       break;
    }
 
-   if (unlikely(intel->always_flush_batch))
+   if (unlikely(brw->always_flush_batch))
       intel_batchbuffer_flush(brw);
 
    /* We've smashed all state compared to what the normal 3D pipeline
@@ -215,7 +213,9 @@ brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
    brw->state.dirty.brw = ~0;
    brw->state.dirty.cache = ~0;
    brw->state_batch_count = 0;
-   intel->batch.need_workaround_flush = true;
+   brw->batch.need_workaround_flush = true;
+   brw->ib.type = -1;
+   intel_batchbuffer_clear_cache(brw);
 
    /* Flush the sampler cache so any texturing from the destination is
     * coherent.