* IN THE SOFTWARE.
*/
+#include "intel_batchbuffer.h"
#include "intel_fbo.h"
#include "brw_blorp.h"
#include "gen6_blorp.h"
#include "gen7_blorp.h"
+#define FILE_DEBUG_FLAG DEBUG_BLORP
+
brw_blorp_mip_info::brw_blorp_mip_info()
: mt(NULL),
level(0),
y1(0),
depth_format(0),
hiz_op(GEN6_HIZ_OP_NONE),
+ fast_clear_op(GEN7_FAST_CLEAR_OP_NONE),
num_samples(0),
use_wm_prog(false)
{
+ color_write_disable[0] = false;
+ color_write_disable[1] = false;
+ color_write_disable[2] = false;
+ color_write_disable[3] = false;
}
extern "C" {
void
-intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
+intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
unsigned int level, unsigned int layer, gen6_hiz_op op)
{
+ const char *opname = NULL;
+
+ switch (op) {
+ case GEN6_HIZ_OP_DEPTH_RESOLVE:
+ opname = "depth resolve";
+ break;
+ case GEN6_HIZ_OP_HIZ_RESOLVE:
+ opname = "hiz ambiguate";
+ break;
+ case GEN6_HIZ_OP_DEPTH_CLEAR:
+ opname = "depth clear";
+ break;
+ case GEN6_HIZ_OP_NONE:
+ opname = "noop?";
+ break;
+ }
+
+ DBG("%s %s to mt %p level %d layer %d\n",
+ __FUNCTION__, opname, mt, level, layer);
+
brw_hiz_op_params params(mt, level, layer, op);
- brw_blorp_exec(intel, ¶ms);
+ brw_blorp_exec(brw, ¶ms);
}
} /* extern "C" */
void
-brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params)
+brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
{
- switch (intel->gen) {
+ switch (brw->gen) {
case 6:
- gen6_blorp_exec(intel, params);
+ gen6_blorp_exec(brw, params);
break;
case 7:
- gen7_blorp_exec(intel, params);
+ gen7_blorp_exec(brw, params);
break;
default:
/* BLORP is not supported before Gen6. */
assert(false);
break;
}
+
+ if (unlikely(brw->always_flush_batch))
+ intel_batchbuffer_flush(brw);
+
+ /* We've smashed all state compared to what the normal 3D pipeline
+ * rendering tracks for GL.
+ */
+ brw->state.dirty.brw = ~0;
+ brw->state.dirty.cache = ~0;
+ brw->state_batch_count = 0;
+ brw->batch.need_workaround_flush = true;
+ brw->ib.type = -1;
+ intel_batchbuffer_clear_cache(brw);
+
+ /* Flush the sampler cache so any texturing from the destination is
+ * coherent.
+ */
+ intel_batchbuffer_emit_mi_flush(brw);
}
brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
x1 = depth.width;
y1 = depth.height;
- assert(mt->hiz_mt != NULL);
+ assert(intel_miptree_slice_has_hiz(mt, level, layer));
switch (mt->format) {
case MESA_FORMAT_Z16: depth_format = BRW_DEPTHFORMAT_D16_UNORM; break;