i965/blorp: Add an is_render_target parameter to surface_info::set.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_blorp.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index a2d02bfc5e0d50752c54133c7611e9a9a03e623c..e519cd91d8ff8456f8f8ac10ea9d7bb85c0b4ec9 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -29,6 +29,8 @@
 #include "gen6_blorp.h"
 #include "gen7_blorp.h"
 
+#define FILE_DEBUG_FLAG DEBUG_BLORP
+
 brw_blorp_mip_info::brw_blorp_mip_info()
    : mt(NULL),
      level(0),
@@ -64,7 +66,8 @@ brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
 void
 brw_blorp_surface_info::set(struct brw_context *brw,
                             struct intel_mipmap_tree *mt,
-                            unsigned int level, unsigned int layer)
+                            unsigned int level, unsigned int layer,
+                            bool is_render_target)
 {
    brw_blorp_mip_info::set(mt, level, layer);
    this->num_samples = mt->num_samples;
@@ -145,6 +148,7 @@ brw_blorp_params::brw_blorp_params()
      y1(0),
      depth_format(0),
      hiz_op(GEN6_HIZ_OP_NONE),
+     fast_clear_op(GEN7_FAST_CLEAR_OP_NONE),
      num_samples(0),
      use_wm_prog(false)
 {
@@ -156,26 +160,44 @@ brw_blorp_params::brw_blorp_params()
 
 extern "C" {
 void
-intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
+intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
               unsigned int level, unsigned int layer, gen6_hiz_op op)
 {
+   const char *opname = NULL;
+
+   switch (op) {
+   case GEN6_HIZ_OP_DEPTH_RESOLVE:
+      opname = "depth resolve";
+      break;
+   case GEN6_HIZ_OP_HIZ_RESOLVE:
+      opname = "hiz ambiguate";
+      break;
+   case GEN6_HIZ_OP_DEPTH_CLEAR:
+      opname = "depth clear";
+      break;
+   case GEN6_HIZ_OP_NONE:
+      opname = "noop?";
+      break;
+   }
+
+   DBG("%s %s to mt %p level %d layer %d\n",
+       __FUNCTION__, opname, mt, level, layer);
+
    brw_hiz_op_params params(mt, level, layer, op);
-   brw_blorp_exec(intel, &params);
+   brw_blorp_exec(brw, &params);
 }
 
 } /* extern "C" */
 
 void
-brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params)
+brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
 {
-   struct brw_context *brw = brw_context(&intel->ctx);
-
-   switch (intel->gen) {
+   switch (brw->gen) {
    case 6:
-      gen6_blorp_exec(intel, params);
+      gen6_blorp_exec(brw, params);
       break;
    case 7:
-      gen7_blorp_exec(intel, params);
+      gen7_blorp_exec(brw, params);
       break;
    default:
       /* BLORP is not supported before Gen6. */
@@ -183,8 +205,8 @@ brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params)
       break;
    }
 
-   if (unlikely(intel->always_flush_batch))
-      intel_batchbuffer_flush(intel);
+   if (unlikely(brw->always_flush_batch))
+      intel_batchbuffer_flush(brw);
 
    /* We've smashed all state compared to what the normal 3D pipeline
     * rendering tracks for GL.
@@ -192,12 +214,14 @@ brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params)
    brw->state.dirty.brw = ~0;
    brw->state.dirty.cache = ~0;
    brw->state_batch_count = 0;
-   intel->batch.need_workaround_flush = true;
+   brw->batch.need_workaround_flush = true;
+   brw->ib.type = -1;
+   intel_batchbuffer_clear_cache(brw);
 
    /* Flush the sampler cache so any texturing from the destination is
     * coherent.
     */
-   intel_batchbuffer_emit_mi_flush(intel);
+   intel_batchbuffer_emit_mi_flush(brw);
 }
 
 brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,