i965: Add an interface for doing hiz ops from C code.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_blorp.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 95f039f63db14d180fe6c5321c94e1c09641d580..fc9b2acbd70e44af117efecff7e3845889fde132 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -35,6 +35,12 @@ brw_blorp_mip_info::brw_blorp_mip_info()
 {
 }
 
+brw_blorp_surface_info::brw_blorp_surface_info()
+   : map_stencil_as_y_tiled(false),
+     num_samples(0)
+{
+}
+
 void
 brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
                         unsigned int level, unsigned int layer)
@@ -46,6 +52,27 @@ brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
    this->layer = layer;
 }
 
+void
+brw_blorp_surface_info::set(struct intel_mipmap_tree *mt,
+                            unsigned int level, unsigned int layer)
+{
+   brw_blorp_mip_info::set(mt, level, layer);
+
+   if (mt->format == MESA_FORMAT_S8) {
+      /* The miptree is a W-tiled stencil buffer.  Surface states can't be set
+       * up for W tiling, so we'll need to use Y tiling and have the WM
+       * program swizzle the coordinates.  Furthermore, we need to set up the
+       * surface state as single-sampled, because the memory layout of related
+       * samples doesn't match between W and Y tiling.
+       */
+      this->map_stencil_as_y_tiled = true;
+      this->num_samples = 0;
+   } else {
+      this->map_stencil_as_y_tiled = false;
+      this->num_samples = mt->num_samples;
+   }
+}
+
 void
 brw_blorp_mip_info::get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const
 {
@@ -65,19 +92,32 @@ brw_blorp_params::brw_blorp_params()
      x1(0),
      y1(0),
      depth_format(0),
-     hiz_op(GEN6_HIZ_OP_NONE)
+     hiz_op(GEN6_HIZ_OP_NONE),
+     num_samples(0),
+     use_wm_prog(false)
 {
 }
 
+extern "C" {
 void
-brw_blorp_params::exec(struct intel_context *intel) const
+intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
+              unsigned int level, unsigned int layer, gen6_hiz_op op)
+{
+   brw_hiz_op_params params(mt, level, layer, op);
+   brw_blorp_exec(intel, &params);
+}
+
+} /* extern "C" */
+
+void
+brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params)
 {
    switch (intel->gen) {
    case 6:
-      gen6_blorp_exec(intel, this);
+      gen6_blorp_exec(intel, params);
       break;
    case 7:
-      gen7_blorp_exec(intel, this);
+      gen7_blorp_exec(intel, params);
       break;
    default:
       /* BLORP is not supported before Gen6. */
@@ -106,3 +146,10 @@ brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
    default:                    assert(0); break;
    }
 }
+
+uint32_t
+brw_hiz_op_params::get_wm_prog(struct brw_context *brw,
+                               brw_blorp_prog_data **prog_data) const
+{
+   return 0;
+}