i965/fs_nir: Get rid of get_alu_src

[mesa.git] / src / mesa / drivers / dri / i965 / brw_blorp.h

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index 85bf099b5de2b9bd6ebb9a7cd3752a94e53519f1..ff68000a2941aec96712dc1ebf34dba9d1f719b1 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -26,6 +26,7 @@
 #include <stdint.h>
 
 #include "brw_context.h"
+#include "brw_reg.h"
 #include "intel_mipmap_tree.h"
 
 struct brw_context;
@@ -38,22 +39,16 @@ void
 brw_blorp_blit_miptrees(struct brw_context *brw,
                         struct intel_mipmap_tree *src_mt,
                         unsigned src_level, unsigned src_layer,
+                        mesa_format src_format,
                         struct intel_mipmap_tree *dst_mt,
                         unsigned dst_level, unsigned dst_layer,
+                        mesa_format dst_format,
                         float src_x0, float src_y0,
                         float src_x1, float src_y1,
                         float dst_x0, float dst_y0,
                         float dst_x1, float dst_y1,
                         GLenum filter, bool mirror_x, bool mirror_y);
 
-bool
-brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,
-                      bool partial_clear);
-
-void
-brw_blorp_resolve_color(struct brw_context *brw,
-                        struct intel_mipmap_tree *mt);
-
 #ifdef __cplusplus
 } /* end extern "C" */
 
@@ -85,6 +80,11 @@ public:
    /**
     * The 2D layer within the miplevel. Combined, level and layer define the
     * 2D miptree slice to use.
+    *
+    * Note: if mt is a 2D multisample array texture on Gen7+ using
+    * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, layer is the physical
+    * layer holding sample 0.  So, for example, if mt->num_samples == 4, then
+    * logical layer n corresponds to layer == 4*n.
     */
    uint32_t layer;
 
@@ -123,17 +123,17 @@ public:
    void set(struct brw_context *brw,
             struct intel_mipmap_tree *mt,
             unsigned int level, unsigned int layer,
-            bool is_render_target);
+            mesa_format format, bool is_render_target);
 
    uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
 
    /* Setting this flag indicates that the buffer's contents are W-tiled
     * stencil data, but the surface state should be set up for Y tiled
-    * MESA_FORMAT_R8 data (this is necessary because surface states don't
+    * MESA_FORMAT_R_UNORM8 data (this is necessary because surface states don't
     * support W tiling).
     *
     * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
-    * MESA_FORMAT_R8 data are 128 pixels wide by 32 pixels high, the width and
+    * MESA_FORMAT_R_UNORM8 data are 128 pixels wide by 32 pixels high, the width and
     * pitch stored in the surface state will be multiplied by 2, and the
     * height will be halved.  Also, since W and Y tiles store their data in a
     * different order, the width and height will be rounded up to a multiple
@@ -144,10 +144,14 @@ public:
 
    unsigned num_samples;
 
-   /* Setting this flag indicates that the surface should be set up in
-    * ARYSPC_LOD0 mode.  Ignored prior to Gen7.
+   /**
+    * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
+    * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
+    *
+    * If ALL_SLICES_AT_EACH_LOD is set, then ARYSPC_LOD0 can be used. Ignored
+    * prior to Gen7.
     */
-   bool array_spacing_lod0;
+   enum miptree_array_layout array_layout;
 
    /**
     * Format that should be used when setting up the surface state for this
@@ -229,7 +233,6 @@ public:
    brw_blorp_surface_info dst;
    enum gen6_hiz_op hiz_op;
    enum gen7_fast_clear_op fast_clear_op;
-   unsigned num_samples;
    bool use_wm_prog;
    brw_blorp_wm_push_constants wm_push_consts;
    bool color_write_disable[4];
@@ -295,7 +298,7 @@ struct brw_blorp_blit_prog_key
    /* Type of the data to be read from the texture (one of
     * BRW_REGISTER_TYPE_{UD,D,F}).
     */
-   unsigned texture_data_type;
+   enum brw_reg_type texture_data_type;
 
    /* True if the source image is W tiled.  If true, the surface state for the
     * source image must be configured as Y tiled, and tex_samples must be 0.
@@ -345,8 +348,10 @@ public:
    brw_blorp_blit_params(struct brw_context *brw,
                          struct intel_mipmap_tree *src_mt,
                          unsigned src_level, unsigned src_layer,
+                         mesa_format src_format,
                          struct intel_mipmap_tree *dst_mt,
                          unsigned dst_level, unsigned dst_layer,
+                         mesa_format dst_format,
                          GLfloat src_x0, GLfloat src_y0,
                          GLfloat src_x1, GLfloat src_y1,
                          GLfloat dst_x0, GLfloat dst_y0,
@@ -415,6 +420,10 @@ gen6_blorp_emit_clip_disable(struct brw_context *brw,
 void
 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
                                   const brw_blorp_params *params);
+
+uint32_t
+gen6_blorp_emit_sampler_state(struct brw_context *brw,
+                              const brw_blorp_params *params);
 /** \} */
 
 #endif /* __cplusplus */