* IN THE SOFTWARE.
*/
+#include "main/context.h"
#include "main/teximage.h"
#include "main/fbobject.h"
-#include "main/renderbuffer.h"
+
+#include "compiler/nir/nir_builder.h"
#include "intel_fbo.h"
return mt;
}
-
-/**
- * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
- * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
- * the physical layer holding sample 0. So, for example, if
- * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
- * 4*n.
- */
-void
-brw_blorp_blit_miptrees(struct brw_context *brw,
- struct intel_mipmap_tree *src_mt,
- unsigned src_level, unsigned src_layer,
- mesa_format src_format,
- struct intel_mipmap_tree *dst_mt,
- unsigned dst_level, unsigned dst_layer,
- mesa_format dst_format,
- float src_x0, float src_y0,
- float src_x1, float src_y1,
- float dst_x0, float dst_y0,
- float dst_x1, float dst_y1,
- GLenum filter, bool mirror_x, bool mirror_y)
+static int
+blorp_get_texture_swizzle(const struct intel_renderbuffer *irb)
{
- /* Get ready to blit. This includes depth resolving the src and dst
- * buffers if necessary. Note: it's not necessary to do a color resolve on
- * the destination buffer because we use the standard render path to render
- * to destination color buffers, and the standard render path is
- * fast-color-aware.
- */
- intel_miptree_resolve_color(brw, src_mt);
- intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_layer);
- intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_layer);
-
- DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
- "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
- __FUNCTION__,
- src_mt->num_samples, _mesa_get_format_name(src_mt->format), src_mt,
- src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
- dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt,
- dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
- mirror_x, mirror_y);
-
- brw_blorp_blit_params params(brw,
- src_mt, src_level, src_layer, src_format,
- dst_mt, dst_level, dst_layer, dst_format,
- src_x0, src_y0,
- src_x1, src_y1,
- dst_x0, dst_y0,
- dst_x1, dst_y1,
- filter, mirror_x, mirror_y);
- brw_blorp_exec(brw, ¶ms);
-
- intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_layer);
+ return irb->Base.Base._BaseFormat == GL_RGB ?
+ MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE) :
+ SWIZZLE_XYZW;
}
static void
struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_irb);
struct intel_mipmap_tree *dst_mt = find_miptree(buffer_bit, dst_irb);
+ const bool es3 = _mesa_is_gles3(&brw->ctx);
/* Do the blit */
brw_blorp_blit_miptrees(brw,
src_mt, src_irb->mt_level, src_irb->mt_layer,
- src_format,
+ src_format, blorp_get_texture_swizzle(src_irb),
dst_mt, dst_irb->mt_level, dst_irb->mt_layer,
dst_format,
srcX0, srcY0, srcX1, srcY1,
dstX0, dstY0, dstX1, dstY1,
- filter, mirror_x, mirror_y);
+ filter, mirror_x, mirror_y,
+ es3, es3);
dst_irb->need_downsample = true;
}
struct intel_renderbuffer *src_irb = intel_renderbuffer(src_rb);
struct intel_texture_image *intel_image = intel_texture_image(dst_image);
+ /* No pixel transfer operations (zoom, bias, mapping), just a blit */
+ if (brw->ctx._ImageTransferState)
+ return false;
+
/* Sync up the state of window system buffers. We need to do this before
* we go looking at the src renderbuffer's miptree.
*/
struct intel_mipmap_tree *src_mt = src_irb->mt;
struct intel_mipmap_tree *dst_mt = intel_image->mt;
- /* BLORP is not supported before Gen6. */
- if (brw->gen < 6 || brw->gen >= 8)
+ /* There is support for only up to eight samples. */
+ if (src_mt->num_samples > 8 || dst_mt->num_samples > 8)
+ return false;
+
+ /* BLORP is only supported from Gen6 onwards. */
+ if (brw->gen < 6)
return false;
if (_mesa_get_format_base_format(src_rb->Format) !=
brw_blorp_blit_miptrees(brw,
src_mt, src_irb->mt_level, src_irb->mt_layer,
- src_rb->Format,
+ src_rb->Format, blorp_get_texture_swizzle(src_irb),
dst_mt, dst_level, dst_slice,
dst_image->TexFormat,
srcX0, srcY0, srcX1, srcY1,
dstX0, dstY0, dstX1, dstY1,
- GL_NEAREST, false, mirror_y);
+ GL_NEAREST, false, mirror_y,
+ false, false);
/* If we're copying to a packed depth stencil texture and the source
* framebuffer has separate stencil, we need to also copy the stencil data
brw_blorp_blit_miptrees(brw,
src_mt, src_irb->mt_level, src_irb->mt_layer,
src_mt->format,
+ blorp_get_texture_swizzle(src_irb),
dst_mt, dst_level, dst_slice,
dst_mt->format,
srcX0, srcY0, srcX1, srcY1,
dstX0, dstY0, dstX1, dstY1,
- GL_NEAREST, false, mirror_y);
+ GL_NEAREST, false, mirror_y,
+ false, false);
}
}
GLbitfield mask, GLenum filter)
{
/* BLORP is not supported before Gen6. */
- if (brw->gen < 6 || brw->gen >= 8)
+ if (brw->gen < 6)
+ return mask;
+
+ /* There is support for only up to eight samples. */
+ if (readFb->Visual.samples > 8 || drawFb->Visual.samples > 8)
return mask;
static GLbitfield buffer_bits[] = {
}
}
- return mask;
+ return mask;
+}
+
+
+/**
+ * Enum to specify the order of arguments in a sampler message
+ */
+enum sampler_message_arg
+{
+ SAMPLER_MESSAGE_ARG_U_FLOAT,
+ SAMPLER_MESSAGE_ARG_V_FLOAT,
+ SAMPLER_MESSAGE_ARG_U_INT,
+ SAMPLER_MESSAGE_ARG_V_INT,
+ SAMPLER_MESSAGE_ARG_R_INT,
+ SAMPLER_MESSAGE_ARG_SI_INT,
+ SAMPLER_MESSAGE_ARG_MCS_INT,
+ SAMPLER_MESSAGE_ARG_ZERO_INT,
+};
+
+struct brw_blorp_blit_vars {
+ /* Uniforms values from brw_blorp_wm_push_constants */
+ nir_variable *u_dst_x0;
+ nir_variable *u_dst_x1;
+ nir_variable *u_dst_y0;
+ nir_variable *u_dst_y1;
+ nir_variable *u_rect_grid_x1;
+ nir_variable *u_rect_grid_y1;
+ struct {
+ nir_variable *multiplier;
+ nir_variable *offset;
+ } u_x_transform, u_y_transform;
+ nir_variable *u_src_z;
+
+ /* gl_FragCoord */
+ nir_variable *frag_coord;
+
+ /* gl_FragColor */
+ nir_variable *color_out;
+};
+
+static void
+brw_blorp_blit_vars_init(nir_builder *b, struct brw_blorp_blit_vars *v,
+ const struct brw_blorp_blit_prog_key *key)
+{
+#define LOAD_UNIFORM(name, type)\
+ v->u_##name = nir_variable_create(b->shader, nir_var_uniform, type, #name); \
+ v->u_##name->data.location = \
+ offsetof(struct brw_blorp_wm_push_constants, name);
+
+ LOAD_UNIFORM(dst_x0, glsl_uint_type())
+ LOAD_UNIFORM(dst_x1, glsl_uint_type())
+ LOAD_UNIFORM(dst_y0, glsl_uint_type())
+ LOAD_UNIFORM(dst_y1, glsl_uint_type())
+ LOAD_UNIFORM(rect_grid_x1, glsl_float_type())
+ LOAD_UNIFORM(rect_grid_y1, glsl_float_type())
+ LOAD_UNIFORM(x_transform.multiplier, glsl_float_type())
+ LOAD_UNIFORM(x_transform.offset, glsl_float_type())
+ LOAD_UNIFORM(y_transform.multiplier, glsl_float_type())
+ LOAD_UNIFORM(y_transform.offset, glsl_float_type())
+ LOAD_UNIFORM(src_z, glsl_uint_type())
+
+#undef DECL_UNIFORM
+
+ v->frag_coord = nir_variable_create(b->shader, nir_var_shader_in,
+ glsl_vec4_type(), "gl_FragCoord");
+ v->frag_coord->data.location = VARYING_SLOT_POS;
+ v->frag_coord->data.origin_upper_left = true;
+
+ v->color_out = nir_variable_create(b->shader, nir_var_shader_out,
+ glsl_vec4_type(), "gl_FragColor");
+ v->color_out->data.location = FRAG_RESULT_COLOR;
+}
+
+nir_ssa_def *
+blorp_blit_get_frag_coords(nir_builder *b,
+ const struct brw_blorp_blit_prog_key *key,
+ struct brw_blorp_blit_vars *v)
+{
+ nir_ssa_def *coord = nir_f2i(b, nir_load_var(b, v->frag_coord));
+
+ if (key->persample_msaa_dispatch) {
+ return nir_vec3(b, nir_channel(b, coord, 0), nir_channel(b, coord, 1),
+ nir_load_system_value(b, nir_intrinsic_load_sample_id, 0));
+ } else {
+ return nir_vec2(b, nir_channel(b, coord, 0), nir_channel(b, coord, 1));
+ }
+}
+
+/**
+ * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
+ * coordinates.
+ */
+nir_ssa_def *
+blorp_blit_apply_transform(nir_builder *b, nir_ssa_def *src_pos,
+ struct brw_blorp_blit_vars *v)
+{
+ nir_ssa_def *offset = nir_vec2(b, nir_load_var(b, v->u_x_transform.offset),
+ nir_load_var(b, v->u_y_transform.offset));
+ nir_ssa_def *mul = nir_vec2(b, nir_load_var(b, v->u_x_transform.multiplier),
+ nir_load_var(b, v->u_y_transform.multiplier));
+
+ return nir_ffma(b, src_pos, mul, offset);
+}
+
+static inline void
+blorp_nir_discard_if_outside_rect(nir_builder *b, nir_ssa_def *pos,
+ struct brw_blorp_blit_vars *v)
+{
+ nir_ssa_def *c0, *c1, *c2, *c3;
+ c0 = nir_ult(b, nir_channel(b, pos, 0), nir_load_var(b, v->u_dst_x0));
+ c1 = nir_uge(b, nir_channel(b, pos, 0), nir_load_var(b, v->u_dst_x1));
+ c2 = nir_ult(b, nir_channel(b, pos, 1), nir_load_var(b, v->u_dst_y0));
+ c3 = nir_uge(b, nir_channel(b, pos, 1), nir_load_var(b, v->u_dst_y1));
+ nir_ssa_def *oob = nir_ior(b, nir_ior(b, c0, c1), nir_ior(b, c2, c3));
+
+ nir_intrinsic_instr *discard =
+ nir_intrinsic_instr_create(b->shader, nir_intrinsic_discard_if);
+ discard->src[0] = nir_src_for_ssa(oob);
+ nir_builder_instr_insert(b, &discard->instr);
+}
+
+static nir_tex_instr *
+blorp_create_nir_tex_instr(nir_shader *shader, nir_texop op,
+ nir_ssa_def *pos, unsigned num_srcs,
+ enum brw_reg_type dst_type)
+{
+ nir_tex_instr *tex = nir_tex_instr_create(shader, num_srcs);
+
+ tex->op = op;
+
+ switch (dst_type) {
+ case BRW_REGISTER_TYPE_F:
+ tex->dest_type = nir_type_float;
+ break;
+ case BRW_REGISTER_TYPE_D:
+ tex->dest_type = nir_type_int;
+ break;
+ case BRW_REGISTER_TYPE_UD:
+ tex->dest_type = nir_type_uint;
+ break;
+ default:
+ unreachable("Invalid texture return type");
+ }
+
+ tex->is_array = false;
+ tex->is_shadow = false;
+
+ /* Blorp only has one texture and it's bound at unit 0 */
+ tex->texture = NULL;
+ tex->sampler = NULL;
+ tex->texture_index = 0;
+ tex->sampler_index = 0;
+
+ nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, NULL);
+
+ return tex;
+}
+
+static nir_ssa_def *
+blorp_nir_tex(nir_builder *b, nir_ssa_def *pos, enum brw_reg_type dst_type)
+{
+ nir_tex_instr *tex =
+ blorp_create_nir_tex_instr(b->shader, nir_texop_tex, pos, 2, dst_type);
+
+ assert(pos->num_components == 2);
+ tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
+ tex->coord_components = 2;
+ tex->src[0].src_type = nir_tex_src_coord;
+ tex->src[0].src = nir_src_for_ssa(pos);
+ tex->src[1].src_type = nir_tex_src_lod;
+ tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
+
+ nir_builder_instr_insert(b, &tex->instr);
+
+ return &tex->dest.ssa;
+}
+
+static nir_ssa_def *
+blorp_nir_txf(nir_builder *b, struct brw_blorp_blit_vars *v,
+ nir_ssa_def *pos, enum brw_reg_type dst_type)
+{
+ nir_tex_instr *tex =
+ blorp_create_nir_tex_instr(b->shader, nir_texop_txf, pos, 2, dst_type);
+
+ /* In order to properly handle 3-D textures, we pull the Z component from
+ * a uniform. TODO: This is a bit magic; we should probably make this
+ * more explicit in the future.
+ */
+ assert(pos->num_components == 2);
+ pos = nir_vec3(b, nir_channel(b, pos, 0), nir_channel(b, pos, 1),
+ nir_load_var(b, v->u_src_z));
+
+ tex->sampler_dim = GLSL_SAMPLER_DIM_3D;
+ tex->coord_components = 3;
+ tex->src[0].src_type = nir_tex_src_coord;
+ tex->src[0].src = nir_src_for_ssa(pos);
+ tex->src[1].src_type = nir_tex_src_lod;
+ tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
+
+ nir_builder_instr_insert(b, &tex->instr);
+
+ return &tex->dest.ssa;
+}
+
+static nir_ssa_def *
+blorp_nir_txf_ms(nir_builder *b, nir_ssa_def *pos, nir_ssa_def *mcs,
+ enum brw_reg_type dst_type)
+{
+ nir_tex_instr *tex =
+ blorp_create_nir_tex_instr(b->shader, nir_texop_txf_ms, pos,
+ mcs != NULL ? 3 : 2, dst_type);
+
+ tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
+ tex->coord_components = 2;
+ tex->src[0].src_type = nir_tex_src_coord;
+ tex->src[0].src = nir_src_for_ssa(pos);
+
+ tex->src[1].src_type = nir_tex_src_ms_index;
+ if (pos->num_components == 2) {
+ tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
+ } else {
+ assert(pos->num_components == 3);
+ tex->src[1].src = nir_src_for_ssa(nir_channel(b, pos, 2));
+ }
+
+ if (mcs) {
+ tex->src[2].src_type = nir_tex_src_ms_mcs;
+ tex->src[2].src = nir_src_for_ssa(mcs);
+ }
+
+ nir_builder_instr_insert(b, &tex->instr);
+
+ return &tex->dest.ssa;
+}
+
+static nir_ssa_def *
+blorp_nir_txf_ms_mcs(nir_builder *b, nir_ssa_def *pos)
+{
+ nir_tex_instr *tex =
+ blorp_create_nir_tex_instr(b->shader, nir_texop_txf_ms_mcs,
+ pos, 1, BRW_REGISTER_TYPE_D);
+
+ tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
+ tex->coord_components = 2;
+ tex->src[0].src_type = nir_tex_src_coord;
+ tex->src[0].src = nir_src_for_ssa(pos);
+
+ nir_builder_instr_insert(b, &tex->instr);
+
+ return &tex->dest.ssa;
+}
+
+static nir_ssa_def *
+nir_mask_shift_or(struct nir_builder *b, nir_ssa_def *dst, nir_ssa_def *src,
+ uint32_t src_mask, int src_left_shift)
+{
+ nir_ssa_def *masked = nir_iand(b, src, nir_imm_int(b, src_mask));
+
+ nir_ssa_def *shifted;
+ if (src_left_shift > 0) {
+ shifted = nir_ishl(b, masked, nir_imm_int(b, src_left_shift));
+ } else if (src_left_shift < 0) {
+ shifted = nir_ushr(b, masked, nir_imm_int(b, -src_left_shift));
+ } else {
+ assert(src_left_shift == 0);
+ shifted = masked;
+ }
+
+ return nir_ior(b, dst, shifted);
+}
+
+/**
+ * Emit code to compensate for the difference between Y and W tiling.
+ *
+ * This code modifies the X and Y coordinates according to the formula:
+ *
+ * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
+ *
+ * (See brw_blorp_build_nir_shader).
+ */
+static inline nir_ssa_def *
+blorp_nir_retile_y_to_w(nir_builder *b, nir_ssa_def *pos)
+{
+ assert(pos->num_components == 2);
+ nir_ssa_def *x_Y = nir_channel(b, pos, 0);
+ nir_ssa_def *y_Y = nir_channel(b, pos, 1);
+
+ /* Given X and Y coordinates that describe an address using Y tiling,
+ * translate to the X and Y coordinates that describe the same address
+ * using W tiling.
+ *
+ * If we break down the low order bits of X and Y, using a
+ * single letter to represent each low-order bit:
+ *
+ * X = A << 7 | 0bBCDEFGH
+ * Y = J << 5 | 0bKLMNP (1)
+ *
+ * Then we can apply the Y tiling formula to see the memory offset being
+ * addressed:
+ *
+ * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
+ *
+ * If we apply the W detiling formula to this memory location, that the
+ * corresponding X' and Y' coordinates are:
+ *
+ * X' = A << 6 | 0bBCDPFH (3)
+ * Y' = J << 6 | 0bKLMNEG
+ *
+ * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
+ * we need to make the following computation:
+ *
+ * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
+ * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
+ */
+ nir_ssa_def *x_W = nir_imm_int(b, 0);
+ x_W = nir_mask_shift_or(b, x_W, x_Y, 0xfffffff4, -1);
+ x_W = nir_mask_shift_or(b, x_W, y_Y, 0x1, 2);
+ x_W = nir_mask_shift_or(b, x_W, x_Y, 0x1, 0);
+
+ nir_ssa_def *y_W = nir_imm_int(b, 0);
+ y_W = nir_mask_shift_or(b, y_W, y_Y, 0xfffffffe, 1);
+ y_W = nir_mask_shift_or(b, y_W, x_Y, 0x8, -2);
+ y_W = nir_mask_shift_or(b, y_W, x_Y, 0x2, -1);
+
+ return nir_vec2(b, x_W, y_W);
+}
+
+/**
+ * Emit code to compensate for the difference between Y and W tiling.
+ *
+ * This code modifies the X and Y coordinates according to the formula:
+ *
+ * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
+ *
+ * (See brw_blorp_build_nir_shader).
+ */
+static inline nir_ssa_def *
+blorp_nir_retile_w_to_y(nir_builder *b, nir_ssa_def *pos)
+{
+ assert(pos->num_components == 2);
+ nir_ssa_def *x_W = nir_channel(b, pos, 0);
+ nir_ssa_def *y_W = nir_channel(b, pos, 1);
+
+ /* Applying the same logic as above, but in reverse, we obtain the
+ * formulas:
+ *
+ * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
+ * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
+ */
+ nir_ssa_def *x_Y = nir_imm_int(b, 0);
+ x_Y = nir_mask_shift_or(b, x_Y, x_W, 0xfffffffa, 1);
+ x_Y = nir_mask_shift_or(b, x_Y, y_W, 0x2, 2);
+ x_Y = nir_mask_shift_or(b, x_Y, y_W, 0x1, 1);
+ x_Y = nir_mask_shift_or(b, x_Y, x_W, 0x1, 0);
+
+ nir_ssa_def *y_Y = nir_imm_int(b, 0);
+ y_Y = nir_mask_shift_or(b, y_Y, y_W, 0xfffffffc, -1);
+ y_Y = nir_mask_shift_or(b, y_Y, x_W, 0x4, -2);
+
+ return nir_vec2(b, x_Y, y_Y);
+}
+
+/**
+ * Emit code to compensate for the difference between MSAA and non-MSAA
+ * surfaces.
+ *
+ * This code modifies the X and Y coordinates according to the formula:
+ *
+ * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
+ *
+ * (See brw_blorp_blit_program).
+ */
+static inline nir_ssa_def *
+blorp_nir_encode_msaa(nir_builder *b, nir_ssa_def *pos,
+ unsigned num_samples, enum intel_msaa_layout layout)
+{
+ assert(pos->num_components == 2 || pos->num_components == 3);
+
+ switch (layout) {
+ case INTEL_MSAA_LAYOUT_NONE:
+ assert(pos->num_components == 2);
+ return pos;
+ case INTEL_MSAA_LAYOUT_CMS:
+ /* We can't compensate for compressed layout since at this point in the
+ * program we haven't read from the MCS buffer.
+ */
+ unreachable("Bad layout in encode_msaa");
+ case INTEL_MSAA_LAYOUT_UMS:
+ /* No translation needed */
+ return pos;
+ case INTEL_MSAA_LAYOUT_IMS: {
+ nir_ssa_def *x_in = nir_channel(b, pos, 0);
+ nir_ssa_def *y_in = nir_channel(b, pos, 1);
+ nir_ssa_def *s_in = pos->num_components == 2 ? nir_imm_int(b, 0) :
+ nir_channel(b, pos, 2);
+
+ nir_ssa_def *x_out = nir_imm_int(b, 0);
+ nir_ssa_def *y_out = nir_imm_int(b, 0);
+ switch (num_samples) {
+ case 2:
+ case 4:
+ /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
+ * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
+ * Y' = Y
+ *
+ * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
+ * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
+ * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
+ */
+ x_out = nir_mask_shift_or(b, x_out, x_in, 0xfffffffe, 1);
+ x_out = nir_mask_shift_or(b, x_out, s_in, 0x1, 1);
+ x_out = nir_mask_shift_or(b, x_out, x_in, 0x1, 0);
+ if (num_samples == 2) {
+ y_out = y_in;
+ } else {
+ y_out = nir_mask_shift_or(b, y_out, y_in, 0xfffffffe, 1);
+ y_out = nir_mask_shift_or(b, y_out, s_in, 0x2, 0);
+ y_out = nir_mask_shift_or(b, y_out, y_in, 0x1, 0);
+ }
+ break;
+
+ case 8:
+ /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
+ * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
+ * | (X & 0b1)
+ * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
+ */
+ x_out = nir_mask_shift_or(b, x_out, x_in, 0xfffffffe, 2);
+ x_out = nir_mask_shift_or(b, x_out, s_in, 0x4, 0);
+ x_out = nir_mask_shift_or(b, x_out, s_in, 0x1, 1);
+ x_out = nir_mask_shift_or(b, x_out, x_in, 0x1, 0);
+ y_out = nir_mask_shift_or(b, y_out, y_in, 0xfffffffe, 1);
+ y_out = nir_mask_shift_or(b, y_out, s_in, 0x2, 0);
+ y_out = nir_mask_shift_or(b, y_out, y_in, 0x1, 0);
+ break;
+
+ default:
+ unreachable("Invalid number of samples for IMS layout");
+ }
+
+ return nir_vec2(b, x_out, y_out);
+ }
+
+ default:
+ unreachable("Invalid MSAA layout");
+ }
+}
+
+/**
+ * Emit code to compensate for the difference between MSAA and non-MSAA
+ * surfaces.
+ *
+ * This code modifies the X and Y coordinates according to the formula:
+ *
+ * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
+ *
+ * (See brw_blorp_blit_program).
+ */
+static inline nir_ssa_def *
+blorp_nir_decode_msaa(nir_builder *b, nir_ssa_def *pos,
+ unsigned num_samples, enum intel_msaa_layout layout)
+{
+ assert(pos->num_components == 2 || pos->num_components == 3);
+
+ switch (layout) {
+ case INTEL_MSAA_LAYOUT_NONE:
+ /* No translation necessary, and S should already be zero. */
+ assert(pos->num_components == 2);
+ return pos;
+ case INTEL_MSAA_LAYOUT_CMS:
+ /* We can't compensate for compressed layout since at this point in the
+ * program we don't have access to the MCS buffer.
+ */
+ unreachable("Bad layout in encode_msaa");
+ case INTEL_MSAA_LAYOUT_UMS:
+ /* No translation necessary. */
+ return pos;
+ case INTEL_MSAA_LAYOUT_IMS: {
+ assert(pos->num_components == 2);
+
+ nir_ssa_def *x_in = nir_channel(b, pos, 0);
+ nir_ssa_def *y_in = nir_channel(b, pos, 1);
+
+ nir_ssa_def *x_out = nir_imm_int(b, 0);
+ nir_ssa_def *y_out = nir_imm_int(b, 0);
+ nir_ssa_def *s_out = nir_imm_int(b, 0);
+ switch (num_samples) {
+ case 2:
+ case 4:
+ /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
+ * where X' = (X & ~0b11) >> 1 | (X & 0b1)
+ * S = (X & 0b10) >> 1
+ *
+ * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
+ * where X' = (X & ~0b11) >> 1 | (X & 0b1)
+ * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
+ * S = (Y & 0b10) | (X & 0b10) >> 1
+ */
+ x_out = nir_mask_shift_or(b, x_out, x_in, 0xfffffffc, -1);
+ x_out = nir_mask_shift_or(b, x_out, x_in, 0x1, 0);
+ if (num_samples == 2) {
+ y_out = y_in;
+ s_out = nir_mask_shift_or(b, s_out, x_in, 0x2, -1);
+ } else {
+ y_out = nir_mask_shift_or(b, y_out, y_in, 0xfffffffc, -1);
+ y_out = nir_mask_shift_or(b, y_out, y_in, 0x1, 0);
+ s_out = nir_mask_shift_or(b, s_out, x_in, 0x2, -1);
+ s_out = nir_mask_shift_or(b, s_out, y_in, 0x2, 0);
+ }
+ break;
+
+ case 8:
+ /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
+ * where X' = (X & ~0b111) >> 2 | (X & 0b1)
+ * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
+ * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
+ */
+ x_out = nir_mask_shift_or(b, x_out, x_in, 0xfffffff8, -2);
+ x_out = nir_mask_shift_or(b, x_out, x_in, 0x1, 0);
+ y_out = nir_mask_shift_or(b, y_out, y_in, 0xfffffffc, -1);
+ y_out = nir_mask_shift_or(b, y_out, y_in, 0x1, 0);
+ s_out = nir_mask_shift_or(b, s_out, x_in, 0x4, 0);
+ s_out = nir_mask_shift_or(b, s_out, y_in, 0x2, 0);
+ s_out = nir_mask_shift_or(b, s_out, x_in, 0x2, -1);
+ break;
+
+ default:
+ unreachable("Invalid number of samples for IMS layout");
+ }
+
+ return nir_vec3(b, x_out, y_out, s_out);
+ }
+
+ default:
+ unreachable("Invalid MSAA layout");
+ }
+}
+
+/**
+ * Count the number of trailing 1 bits in the given value. For example:
+ *
+ * count_trailing_one_bits(0) == 0
+ * count_trailing_one_bits(7) == 3
+ * count_trailing_one_bits(11) == 2
+ */
+static inline int count_trailing_one_bits(unsigned value)
+{
+#ifdef HAVE___BUILTIN_CTZ
+ return __builtin_ctz(~value);
+#else
+ return _mesa_bitcount(value & ~(value + 1));
+#endif
+}
+
+static nir_ssa_def *
+blorp_nir_manual_blend_average(nir_builder *b, nir_ssa_def *pos,
+ unsigned tex_samples,
+ enum intel_msaa_layout tex_layout,
+ enum brw_reg_type dst_type)
+{
+ /* If non-null, this is the outer-most if statement */
+ nir_if *outer_if = NULL;
+
+ nir_variable *color =
+ nir_local_variable_create(b->impl, glsl_vec4_type(), "color");
+
+ nir_ssa_def *mcs = NULL;
+ if (tex_layout == INTEL_MSAA_LAYOUT_CMS)
+ mcs = blorp_nir_txf_ms_mcs(b, pos);
+
+ /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
+ *
+ * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
+ *
+ * This ensures that when all samples have the same value, no numerical
+ * precision is lost, since each addition operation always adds two equal
+ * values, and summing two equal floating point values does not lose
+ * precision.
+ *
+ * We perform this computation by treating the texture_data array as a
+ * stack and performing the following operations:
+ *
+ * - push sample 0 onto stack
+ * - push sample 1 onto stack
+ * - add top two stack entries
+ * - push sample 2 onto stack
+ * - push sample 3 onto stack
+ * - add top two stack entries
+ * - add top two stack entries
+ * - divide top stack entry by 4
+ *
+ * Note that after pushing sample i onto the stack, the number of add
+ * operations we do is equal to the number of trailing 1 bits in i. This
+ * works provided the total number of samples is a power of two, which it
+ * always is for i965.
+ *
+ * For integer formats, we replace the add operations with average
+ * operations and skip the final division.
+ */
+ nir_ssa_def *texture_data[4];
+ unsigned stack_depth = 0;
+ for (unsigned i = 0; i < tex_samples; ++i) {
+ assert(stack_depth == _mesa_bitcount(i)); /* Loop invariant */
+
+ /* Push sample i onto the stack */
+ assert(stack_depth < ARRAY_SIZE(texture_data));
+
+ nir_ssa_def *ms_pos = nir_vec3(b, nir_channel(b, pos, 0),
+ nir_channel(b, pos, 1),
+ nir_imm_int(b, i));
+ texture_data[stack_depth++] = blorp_nir_txf_ms(b, ms_pos, mcs, dst_type);
+
+ if (i == 0 && tex_layout == INTEL_MSAA_LAYOUT_CMS) {
+ /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
+ * suggests an optimization:
+ *
+ * "A simple optimization with probable large return in
+ * performance is to compare the MCS value to zero (indicating
+ * all samples are on sample slice 0), and sample only from
+ * sample slice 0 using ld2dss if MCS is zero."
+ *
+ * Note that in the case where the MCS value is zero, sampling from
+ * sample slice 0 using ld2dss and sampling from sample 0 using
+ * ld2dms are equivalent (since all samples are on sample slice 0).
+ * Since we have already sampled from sample 0, all we need to do is
+ * skip the remaining fetches and averaging if MCS is zero.
+ */
+ nir_ssa_def *mcs_zero =
+ nir_ieq(b, nir_channel(b, mcs, 0), nir_imm_int(b, 0));
+ nir_if *if_stmt = nir_if_create(b->shader);
+ if_stmt->condition = nir_src_for_ssa(mcs_zero);
+ nir_cf_node_insert(b->cursor, &if_stmt->cf_node);
+
+ b->cursor = nir_after_cf_list(&if_stmt->then_list);
+ nir_store_var(b, color, texture_data[0], 0xf);
+
+ b->cursor = nir_after_cf_list(&if_stmt->else_list);
+ outer_if = if_stmt;
+ }
+
+ for (int j = 0; j < count_trailing_one_bits(i); j++) {
+ assert(stack_depth >= 2);
+ --stack_depth;
+
+ assert(dst_type == BRW_REGISTER_TYPE_F);
+ texture_data[stack_depth - 1] =
+ nir_fadd(b, texture_data[stack_depth - 1],
+ texture_data[stack_depth]);
+ }
+ }
+
+ /* We should have just 1 sample on the stack now. */
+ assert(stack_depth == 1);
+
+ texture_data[0] = nir_fmul(b, texture_data[0],
+ nir_imm_float(b, 1.0 / tex_samples));
+
+ nir_store_var(b, color, texture_data[0], 0xf);
+
+ if (outer_if)
+ b->cursor = nir_after_cf_node(&outer_if->cf_node);
+
+ return nir_load_var(b, color);
+}
+
+static inline nir_ssa_def *
+nir_imm_vec2(nir_builder *build, float x, float y)
+{
+ nir_const_value v;
+
+ memset(&v, 0, sizeof(v));
+ v.f32[0] = x;
+ v.f32[1] = y;
+
+ return nir_build_imm(build, 4, 32, v);
+}
+
+static nir_ssa_def *
+blorp_nir_manual_blend_bilinear(nir_builder *b, nir_ssa_def *pos,
+ unsigned tex_samples,
+ const brw_blorp_blit_prog_key *key,
+ struct brw_blorp_blit_vars *v)
+{
+ nir_ssa_def *pos_xy = nir_channels(b, pos, 0x3);
+
+ nir_ssa_def *scale = nir_imm_vec2(b, key->x_scale, key->y_scale);
+
+ /* Translate coordinates to lay out the samples in a rectangular grid
+ * roughly corresponding to sample locations.
+ */
+ pos_xy = nir_fmul(b, pos_xy, scale);
+ /* Adjust coordinates so that integers represent pixel centers rather
+ * than pixel edges.
+ */
+ pos_xy = nir_fadd(b, pos_xy, nir_imm_float(b, -0.5));
+ /* Clamp the X, Y texture coordinates to properly handle the sampling of
+ * texels on texture edges.
+ */
+ pos_xy = nir_fmin(b, nir_fmax(b, pos_xy, nir_imm_float(b, 0.0)),
+ nir_vec2(b, nir_load_var(b, v->u_rect_grid_x1),
+ nir_load_var(b, v->u_rect_grid_y1)));
+
+ /* Store the fractional parts to be used as bilinear interpolation
+ * coefficients.
+ */
+ nir_ssa_def *frac_xy = nir_ffract(b, pos_xy);
+ /* Round the float coordinates down to nearest integer */
+ pos_xy = nir_fdiv(b, nir_ftrunc(b, pos_xy), scale);
+
+ nir_ssa_def *tex_data[4];
+ for (unsigned i = 0; i < 4; ++i) {
+ float sample_off_x = (float)(i & 0x1) / key->x_scale;
+ float sample_off_y = (float)((i >> 1) & 0x1) / key->y_scale;
+ nir_ssa_def *sample_off = nir_imm_vec2(b, sample_off_x, sample_off_y);
+
+ nir_ssa_def *sample_coords = nir_fadd(b, pos_xy, sample_off);
+ nir_ssa_def *sample_coords_int = nir_f2i(b, sample_coords);
+
+ /* The MCS value we fetch has to match up with the pixel that we're
+ * sampling from. Since we sample from different pixels in each
+ * iteration of this "for" loop, the call to mcs_fetch() should be
+ * here inside the loop after computing the pixel coordinates.
+ */
+ nir_ssa_def *mcs = NULL;
+ if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS)
+ mcs = blorp_nir_txf_ms_mcs(b, sample_coords_int);
+
+ /* Compute sample index and map the sample index to a sample number.
+ * Sample index layout shows the numbering of slots in a rectangular
+ * grid of samples with in a pixel. Sample number layout shows the
+ * rectangular grid of samples roughly corresponding to the real sample
+ * locations with in a pixel.
+ * In case of 4x MSAA, layout of sample indices matches the layout of
+ * sample numbers:
+ * ---------
+ * | 0 | 1 |
+ * ---------
+ * | 2 | 3 |
+ * ---------
+ *
+ * In case of 8x MSAA the two layouts don't match.
+ * sample index layout : --------- sample number layout : ---------
+ * | 0 | 1 | | 5 | 2 |
+ * --------- ---------
+ * | 2 | 3 | | 4 | 6 |
+ * --------- ---------
+ * | 4 | 5 | | 0 | 3 |
+ * --------- ---------
+ * | 6 | 7 | | 7 | 1 |
+ * --------- ---------
+ *
+ * Fortunately, this can be done fairly easily as:
+ * S' = (0x17306425 >> (S * 4)) & 0xf
+ */
+ nir_ssa_def *frac = nir_ffract(b, sample_coords);
+ nir_ssa_def *sample =
+ nir_fdot2(b, frac, nir_imm_vec2(b, key->x_scale,
+ key->x_scale * key->y_scale));
+ sample = nir_f2i(b, sample);
+
+ if (tex_samples == 8) {
+ sample = nir_iand(b, nir_ishr(b, nir_imm_int(b, 0x17306425),
+ nir_ishl(b, sample, nir_imm_int(b, 2))),
+ nir_imm_int(b, 0xf));
+ }
+ nir_ssa_def *pos_ms = nir_vec3(b, nir_channel(b, sample_coords_int, 0),
+ nir_channel(b, sample_coords_int, 1),
+ sample);
+ tex_data[i] = blorp_nir_txf_ms(b, pos_ms, mcs, key->texture_data_type);
+ }
+
+ nir_ssa_def *frac_x = nir_channel(b, frac_xy, 0);
+ nir_ssa_def *frac_y = nir_channel(b, frac_xy, 1);
+ return nir_flrp(b, nir_flrp(b, tex_data[0], tex_data[1], frac_x),
+ nir_flrp(b, tex_data[2], tex_data[3], frac_x),
+ frac_y);
}
-
-/**
- * Enum to specify the order of arguments in a sampler message
- */
-enum sampler_message_arg
-{
- SAMPLER_MESSAGE_ARG_U_FLOAT,
- SAMPLER_MESSAGE_ARG_V_FLOAT,
- SAMPLER_MESSAGE_ARG_U_INT,
- SAMPLER_MESSAGE_ARG_V_INT,
- SAMPLER_MESSAGE_ARG_SI_INT,
- SAMPLER_MESSAGE_ARG_MCS_INT,
- SAMPLER_MESSAGE_ARG_ZERO_INT,
-};
-
/**
* Generator for WM programs used in BLORP blits.
*
* (In these formulas, pitch is the number of bytes occupied by a single row
* of samples).
*/
+static nir_shader *
+brw_blorp_build_nir_shader(struct brw_context *brw,
+ const brw_blorp_blit_prog_key *key,
+ struct brw_blorp_prog_data *prog_data)
+{
+ nir_ssa_def *src_pos, *dst_pos, *color;
+
+ /* Sanity checks */
+ if (key->dst_tiled_w && key->rt_samples > 0) {
+ /* If the destination image is W tiled and multisampled, then the thread
+ * must be dispatched once per sample, not once per pixel. This is
+ * necessary because after conversion between W and Y tiling, there's no
+ * guarantee that all samples corresponding to a single pixel will still
+ * be together.
+ */
+ assert(key->persample_msaa_dispatch);
+ }
+
+ if (key->blend) {
+ /* We are blending, which means we won't have an opportunity to
+ * translate the tiling and sample count for the texture surface. So
+ * the surface state for the texture must be configured with the correct
+ * tiling and sample count.
+ */
+ assert(!key->src_tiled_w);
+ assert(key->tex_samples == key->src_samples);
+ assert(key->tex_layout == key->src_layout);
+ assert(key->tex_samples > 0);
+ }
+
+ if (key->persample_msaa_dispatch) {
+ /* It only makes sense to do persample dispatch if the render target is
+ * configured as multisampled.
+ */
+ assert(key->rt_samples > 0);
+ }
+
+ /* Make sure layout is consistent with sample count */
+ assert((key->tex_layout == INTEL_MSAA_LAYOUT_NONE) ==
+ (key->tex_samples == 0));
+ assert((key->rt_layout == INTEL_MSAA_LAYOUT_NONE) ==
+ (key->rt_samples == 0));
+ assert((key->src_layout == INTEL_MSAA_LAYOUT_NONE) ==
+ (key->src_samples == 0));
+ assert((key->dst_layout == INTEL_MSAA_LAYOUT_NONE) ==
+ (key->dst_samples == 0));
+
+ /* Set up prog_data */
+ brw_blorp_prog_data_init(prog_data);
+
+ nir_builder b;
+ nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
+
+ struct brw_blorp_blit_vars v;
+ brw_blorp_blit_vars_init(&b, &v, key);
+
+ dst_pos = blorp_blit_get_frag_coords(&b, key, &v);
+
+ /* Render target and texture hardware don't support W tiling until Gen8. */
+ const bool rt_tiled_w = false;
+ const bool tex_tiled_w = brw->gen >= 8 && key->src_tiled_w;
+
+ /* The address that data will be written to is determined by the
+ * coordinates supplied to the WM thread and the tiling and sample count of
+ * the render target, according to the formula:
+ *
+ * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
+ *
+ * If the actual tiling and sample count of the destination surface are not
+ * the same as the configuration of the render target, then these
+ * coordinates are wrong and we have to adjust them to compensate for the
+ * difference.
+ */
+ if (rt_tiled_w != key->dst_tiled_w ||
+ key->rt_samples != key->dst_samples ||
+ key->rt_layout != key->dst_layout) {
+ dst_pos = blorp_nir_encode_msaa(&b, dst_pos, key->rt_samples,
+ key->rt_layout);
+ /* Now (X, Y, S) = detile(rt_tiling, offset) */
+ if (rt_tiled_w != key->dst_tiled_w)
+ dst_pos = blorp_nir_retile_y_to_w(&b, dst_pos);
+ /* Now (X, Y, S) = detile(rt_tiling, offset) */
+ dst_pos = blorp_nir_decode_msaa(&b, dst_pos, key->dst_samples,
+ key->dst_layout);
+ }
+
+ /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
+ *
+ * That is: X, Y and S now contain the true coordinates and sample index of
+ * the data that the WM thread should output.
+ *
+ * If we need to kill pixels that are outside the destination rectangle,
+ * now is the time to do it.
+ */
+ if (key->use_kill)
+ blorp_nir_discard_if_outside_rect(&b, dst_pos, &v);
+
+ src_pos = blorp_blit_apply_transform(&b, nir_i2f(&b, dst_pos), &v);
+ if (dst_pos->num_components == 3) {
+ /* The sample coordinate is an integer that we want left alone but
+ * blorp_blit_apply_transform() blindly applies the transform to all
+ * three coordinates. Grab the original sample index.
+ */
+ src_pos = nir_vec3(&b, nir_channel(&b, src_pos, 0),
+ nir_channel(&b, src_pos, 1),
+ nir_channel(&b, dst_pos, 2));
+ }
+
+ /* If the source image is not multisampled, then we want to fetch sample
+ * number 0, because that's the only sample there is.
+ */
+ if (key->src_samples == 0)
+ src_pos = nir_channels(&b, src_pos, 0x3);
+
+ /* X, Y, and S are now the coordinates of the pixel in the source image
+ * that we want to texture from. Exception: if we are blending, then S is
+ * irrelevant, because we are going to fetch all samples.
+ */
+ if (key->blend && !key->blit_scaled) {
+ /* Resolves (effecively) use texelFetch, so we need integers and we
+ * don't care about the sample index if we got one.
+ */
+ src_pos = nir_f2i(&b, nir_channels(&b, src_pos, 0x3));
+
+ if (brw->gen == 6) {
+ /* Because gen6 only supports 4x interleved MSAA, we can do all the
+ * blending we need with a single linear-interpolated texture lookup
+ * at the center of the sample. The texture coordinates to be odd
+ * integers so that they correspond to the center of a 2x2 block
+ * representing the four samples that maxe up a pixel. So we need
+ * to multiply our X and Y coordinates each by 2 and then add 1.
+ */
+ src_pos = nir_ishl(&b, src_pos, nir_imm_int(&b, 1));
+ src_pos = nir_iadd(&b, src_pos, nir_imm_int(&b, 1));
+ src_pos = nir_i2f(&b, src_pos);
+ color = blorp_nir_tex(&b, src_pos, key->texture_data_type);
+ } else {
+ /* Gen7+ hardware doesn't automaticaly blend. */
+ color = blorp_nir_manual_blend_average(&b, src_pos, key->src_samples,
+ key->src_layout,
+ key->texture_data_type);
+ }
+ } else if (key->blend && key->blit_scaled) {
+ color = blorp_nir_manual_blend_bilinear(&b, src_pos, key->src_samples, key, &v);
+ } else {
+ if (key->bilinear_filter) {
+ color = blorp_nir_tex(&b, src_pos, key->texture_data_type);
+ } else {
+ /* We're going to use texelFetch, so we need integers */
+ if (src_pos->num_components == 2) {
+ src_pos = nir_f2i(&b, src_pos);
+ } else {
+ assert(src_pos->num_components == 3);
+ src_pos = nir_vec3(&b, nir_channel(&b, nir_f2i(&b, src_pos), 0),
+ nir_channel(&b, nir_f2i(&b, src_pos), 1),
+ nir_channel(&b, src_pos, 2));
+ }
+
+ /* We aren't blending, which means we just want to fetch a single
+ * sample from the source surface. The address that we want to fetch
+ * from is related to the X, Y and S values according to the formula:
+ *
+ * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
+ *
+ * If the actual tiling and sample count of the source surface are
+ * not the same as the configuration of the texture, then we need to
+ * adjust the coordinates to compensate for the difference.
+ */
+ if (tex_tiled_w != key->src_tiled_w ||
+ key->tex_samples != key->src_samples ||
+ key->tex_layout != key->src_layout) {
+ src_pos = blorp_nir_encode_msaa(&b, src_pos, key->src_samples,
+ key->src_layout);
+ /* Now (X, Y, S) = detile(src_tiling, offset) */
+ if (tex_tiled_w != key->src_tiled_w)
+ src_pos = blorp_nir_retile_w_to_y(&b, src_pos);
+ /* Now (X, Y, S) = detile(tex_tiling, offset) */
+ src_pos = blorp_nir_decode_msaa(&b, src_pos, key->tex_samples,
+ key->tex_layout);
+ }
+
+ /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
+ *
+ * In other words: X, Y, and S now contain values which, when passed to
+ * the texturing unit, will cause data to be read from the correct
+ * memory location. So we can fetch the texel now.
+ */
+ if (key->src_samples == 0) {
+ color = blorp_nir_txf(&b, &v, src_pos, key->texture_data_type);
+ } else {
+ nir_ssa_def *mcs = NULL;
+ if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS)
+ mcs = blorp_nir_txf_ms_mcs(&b, src_pos);
+
+ color = blorp_nir_txf_ms(&b, src_pos, mcs, key->texture_data_type);
+ }
+ }
+ }
+
+ nir_store_var(&b, v.color_out, color, 0xf);
+
+ return b.shader;
+}
+
class brw_blorp_blit_program : public brw_blorp_eu_emitter
{
public:
brw_blorp_blit_program(struct brw_context *brw,
- const brw_blorp_blit_prog_key *key, bool debug_flag);
+ const brw_blorp_blit_prog_key *key);
- const GLuint *compile(struct brw_context *brw, GLuint *program_size);
+ const GLuint *compile(struct brw_context *brw, bool debug_flag,
+ GLuint *program_size);
brw_blorp_prog_data prog_data;
struct brw_reg multiplier;
struct brw_reg offset;
} x_transform, y_transform;
+ struct brw_reg src_z;
/* Data read from texture (4 vec16's per array element) */
struct brw_reg texture_data[LOG2_MAX_BLEND_SAMPLES + 1];
};
brw_blorp_blit_program::brw_blorp_blit_program(
- struct brw_context *brw,
- const brw_blorp_blit_prog_key *key,
- bool debug_flag)
- : brw_blorp_eu_emitter(brw, debug_flag),
- brw(brw),
- key(key)
+ struct brw_context *brw, const brw_blorp_blit_prog_key *key)
+ : brw_blorp_eu_emitter(), brw(brw), key(key)
{
}
const GLuint *
-brw_blorp_blit_program::compile(struct brw_context *brw,
+brw_blorp_blit_program::compile(struct brw_context *brw, bool debug_flag,
GLuint *program_size)
{
/* Sanity checks */
(key->dst_samples == 0));
/* Set up prog_data */
- memset(&prog_data, 0, sizeof(prog_data));
+ brw_blorp_prog_data_init(&prog_data);
prog_data.persample_msaa_dispatch = key->persample_msaa_dispatch;
alloc_regs();
compute_frag_coords();
- /* Render target and texture hardware don't support W tiling. */
+ /* Render target and texture hardware don't support W tiling until Gen8. */
const bool rt_tiled_w = false;
- const bool tex_tiled_w = false;
+ const bool tex_tiled_w = brw->gen >= 8 && key->src_tiled_w;
/* The address that data will be written to is determined by the
* coordinates supplied to the WM thread and the tiling and sample count of
*/
render_target_write();
- return get_program(program_size);
+ return get_program(brw, debug_flag, program_size);
}
void
ALLOC_REG(x_transform.offset, BRW_REGISTER_TYPE_F);
ALLOC_REG(y_transform.multiplier, BRW_REGISTER_TYPE_F);
ALLOC_REG(y_transform.offset, BRW_REGISTER_TYPE_F);
+ ALLOC_REG(src_z, BRW_REGISTER_TYPE_UD);
#undef CONST_LOC
#undef ALLOC_REG
}
int reg = 0;
this->R0 = retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW);
this->R1 = retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW);
- prog_data.first_curbe_grf = reg;
+ prog_data.first_curbe_grf_0 = reg;
alloc_push_const_regs(reg);
reg += BRW_BLORP_NUM_PUSH_CONST_REGS;
for (unsigned i = 0; i < ARRAY_SIZE(texture_data); ++i) {
if (key->persample_msaa_dispatch) {
switch (key->rt_samples) {
+ case 2:
case 4: {
/* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
* Therefore, subspan 0 will represent sample 0, subspan 1 will
* then copy from it using vstride=1, width=4, hstride=0.
*/
struct brw_reg t1_uw1 = retype(t1, BRW_REGISTER_TYPE_UW);
- emit_mov(vec16(t1_uw1), brw_imm_v(0x3210));
+ emit_mov(vec16(t1_uw1), key->rt_samples == 4 ?
+ brw_imm_v(0x3210) : brw_imm_v(0x1010));
/* Move to UD sample_index register. */
emit_mov_8(S, stride(t1_uw1, 1, 4, 0));
emit_mov_8(offset(S, 1), suboffset(stride(t1_uw1, 1, 4, 0), 2));
break;
case INTEL_MSAA_LAYOUT_IMS:
switch (num_samples) {
+ case 2:
+ /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
+ * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
+ * Y' = Y
+ */
case 4:
/* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
* where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
}
emit_shl(t1, t1, brw_imm_uw(1)); /* (X & ~0b1) << 1
| (S & 0b1) << 1 */
+ if (num_samples == 2) {
+ emit_mov(Yp, Y);
+ return;
+ }
+
emit_and(t2, X, brw_imm_uw(1)); /* X & 0b1 */
emit_or(Xp, t1, t2);
emit_and(t1, Y, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
case INTEL_MSAA_LAYOUT_IMS:
assert(s_is_zero);
switch (num_samples) {
+ case 2:
+ /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
+ * where X' = (X & ~0b11) >> 1 | (X & 0b1)
+ * S = (X & 0b10) >> 1
+ */
case 4:
/* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
* where X' = (X & ~0b11) >> 1 | (X & 0b1)
emit_shr(t1, t1, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
emit_and(t2, X, brw_imm_uw(1)); /* X & 0b1 */
emit_or(Xp, t1, t2);
- emit_and(t1, Y, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
- emit_shr(t1, t1, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
- emit_and(t2, Y, brw_imm_uw(1)); /* Y & 0b1 */
- emit_or(Yp, t1, t2);
- emit_and(t1, Y, brw_imm_uw(2)); /* Y & 0b10 */
- emit_and(t2, X, brw_imm_uw(2)); /* X & 0b10 */
- emit_shr(t2, t2, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
- emit_or(S, t1, t2);
+
+ if (num_samples == 2) {
+ emit_mov(Yp, Y);
+ emit_and(t2, X, brw_imm_uw(2)); /* X & 0b10 */
+ emit_shr(S, t2, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
+ } else {
+ emit_and(t1, Y, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
+ emit_shr(t1, t1, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
+ emit_and(t2, Y, brw_imm_uw(1)); /* Y & 0b1 */
+ emit_or(Yp, t1, t2);
+ emit_and(t1, Y, brw_imm_uw(2)); /* Y & 0b10 */
+ emit_and(t2, X, brw_imm_uw(2)); /* X & 0b10 */
+ emit_shr(t2, t2, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
+ emit_or(S, t1, t2);
+ }
break;
case 8:
/* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
/* Round the float coordinates down to nearest integer */
emit_rndd(Xp_f, X_f);
emit_rndd(Yp_f, Y_f);
- emit_mul(X_f, Xp_f, brw_imm_f(1 / key->x_scale));
- emit_mul(Y_f, Yp_f, brw_imm_f(1 / key->y_scale));
+ emit_mul(X_f, Xp_f, brw_imm_f(1.0f / key->x_scale));
+ emit_mul(Y_f, Yp_f, brw_imm_f(1.0f / key->y_scale));
SWAP_XY_AND_XPYP();
} else if (!key->bilinear_filter) {
/* Round the float coordinates down to nearest integer by moving to
emit_min(regY, regY, clampY1);
}
-/**
- * Emit code to transform the X and Y coordinates as needed for blending
- * together the different samples in an MSAA texture.
- */
-void
-brw_blorp_blit_program::single_to_blend()
-{
- /* When looking up samples in an MSAA texture using the SAMPLE message,
- * Gen6 requires the texture coordinates to be odd integers (so that they
- * correspond to the center of a 2x2 block representing the four samples
- * that maxe up a pixel). So we need to multiply our X and Y coordinates
- * each by 2 and then add 1.
- */
- emit_shl(t1, X, brw_imm_w(1));
- emit_shl(t2, Y, brw_imm_w(1));
- emit_add(Xp, t1, brw_imm_w(1));
- emit_add(Yp, t2, brw_imm_w(1));
- SWAP_XY_AND_XPYP();
-}
-
-
-/**
- * Count the number of trailing 1 bits in the given value. For example:
- *
- * count_trailing_one_bits(0) == 0
- * count_trailing_one_bits(7) == 3
- * count_trailing_one_bits(11) == 2
- */
-inline int count_trailing_one_bits(unsigned value)
-{
-#ifdef HAVE___BUILTIN_CTZ
- return __builtin_ctz(~value);
-#else
- return _mesa_bitcount(value & ~(value + 1));
-#endif
-}
void
if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS)
mcs_fetch();
+ assert(key->texture_data_type == BRW_REGISTER_TYPE_F);
+
/* We add together samples using a binary tree structure, e.g. for 4x MSAA:
*
* result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
/* TODO: should use a smaller loop bound for non_RGBA formats */
for (int k = 0; k < 4; ++k) {
- emit_combine(key->texture_data_type == BRW_REGISTER_TYPE_F ?
- BRW_OPCODE_ADD : BRW_OPCODE_AVG,
+ emit_combine(BRW_OPCODE_ADD,
offset(texture_data[stack_depth - 1], 2*k),
offset(vec8(texture_data[stack_depth - 1]), 2*k),
offset(vec8(texture_data[stack_depth]), 2*k));
/* We should have just 1 sample on the stack now. */
assert(stack_depth == 1);
- if (key->texture_data_type == BRW_REGISTER_TYPE_F) {
- /* Scale the result down by a factor of num_samples */
- /* TODO: should use a smaller loop bound for non-RGBA formats */
- for (int j = 0; j < 4; ++j) {
- emit_mul(offset(texture_data[0], 2*j),
- offset(vec8(texture_data[0]), 2*j),
- brw_imm_f(1.0/num_samples));
- }
+ /* Scale the result down by a factor of num_samples */
+ /* TODO: should use a smaller loop bound for non-RGBA formats */
+ for (int j = 0; j < 4; ++j) {
+ emit_mul(offset(texture_data[0], 2*j),
+ offset(vec8(texture_data[0]), 2*j),
+ brw_imm_f(1.0f / num_samples));
}
if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS)
/* Compute pixel coordinates */
emit_add(vec16(x_sample_coords), Xp_f,
- brw_imm_f((float)(i & 0x1) * (1.0 / key->x_scale)));
+ brw_imm_f((float)(i & 0x1) * (1.0f / key->x_scale)));
emit_add(vec16(y_sample_coords), Yp_f,
- brw_imm_f((float)((i >> 1) & 0x1) * (1.0 / key->y_scale)));
+ brw_imm_f((float)((i >> 1) & 0x1) * (1.0f / key->y_scale)));
emit_mov(vec16(X), x_sample_coords);
emit_mov(vec16(Y), y_sample_coords);
* --------- ---------
* | 6 | 7 | | 7 | 1 |
* --------- ---------
+ *
+ * Fortunately, this can be done fairly easily as:
+ * S' = (0x17306425 >> (S * 4)) & 0xf
*/
emit_frc(vec16(t1_f), x_sample_coords);
emit_frc(vec16(t2_f), y_sample_coords);
emit_mov(vec16(S), t1_f);
if (num_samples == 8) {
- /* Map the sample index to a sample number */
- emit_cmp_if(BRW_CONDITIONAL_L, S, brw_imm_d(4));
- {
- emit_mov(vec16(t2), brw_imm_d(5));
- emit_if_eq_mov(S, 1, vec16(t2), 2);
- emit_if_eq_mov(S, 2, vec16(t2), 4);
- emit_if_eq_mov(S, 3, vec16(t2), 6);
- }
- emit_else();
- {
- emit_mov(vec16(t2), brw_imm_d(0));
- emit_if_eq_mov(S, 5, vec16(t2), 3);
- emit_if_eq_mov(S, 6, vec16(t2), 7);
- emit_if_eq_mov(S, 7, vec16(t2), 1);
- }
- emit_endif();
- emit_mov(vec16(S), t2);
+ emit_mov(vec16(t2), brw_imm_d(0x17306425));
+ emit_shl(vec16(S), S, brw_imm_d(2));
+ emit_shr(vec16(S), t2, S);
+ emit_and(vec16(S), S, brw_imm_d(0xf));
}
texel_fetch(texture_data[i]);
}
SAMPLER_MESSAGE_ARG_ZERO_INT, /* LOD */
SAMPLER_MESSAGE_ARG_SI_INT
};
- static const sampler_message_arg gen7_ld_args[3] = {
+ static const sampler_message_arg gen7_ld_args[] = {
SAMPLER_MESSAGE_ARG_U_INT,
SAMPLER_MESSAGE_ARG_ZERO_INT, /* LOD */
- SAMPLER_MESSAGE_ARG_V_INT
+ SAMPLER_MESSAGE_ARG_V_INT,
+ SAMPLER_MESSAGE_ARG_R_INT
};
static const sampler_message_arg gen7_ld2dss_args[3] = {
SAMPLER_MESSAGE_ARG_SI_INT,
SAMPLER_MESSAGE_ARG_U_INT,
SAMPLER_MESSAGE_ARG_V_INT
};
+ static const sampler_message_arg gen9_ld_args[] = {
+ SAMPLER_MESSAGE_ARG_U_INT,
+ SAMPLER_MESSAGE_ARG_V_INT,
+ SAMPLER_MESSAGE_ARG_ZERO_INT, /* LOD */
+ SAMPLER_MESSAGE_ARG_R_INT
+ };
switch (brw->gen) {
case 6:
texture_lookup(dst, SHADER_OPCODE_TXF, gen6_args, s_is_zero ? 2 : 5);
break;
case 7:
+ case 8:
+ case 9:
switch (key->tex_layout) {
case INTEL_MSAA_LAYOUT_IMS:
/* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
break;
case INTEL_MSAA_LAYOUT_NONE:
assert(s_is_zero);
- texture_lookup(dst, SHADER_OPCODE_TXF, gen7_ld_args,
- ARRAY_SIZE(gen7_ld_args));
+ if (brw->gen < 9) {
+ texture_lookup(dst, SHADER_OPCODE_TXF, gen7_ld_args,
+ ARRAY_SIZE(gen7_ld_args));
+ } else {
+ texture_lookup(dst, SHADER_OPCODE_TXF, gen9_ld_args,
+ ARRAY_SIZE(gen9_ld_args));
+ }
break;
}
break;
case SAMPLER_MESSAGE_ARG_V_INT:
emit_mov(mrf, Y);
break;
+ case SAMPLER_MESSAGE_ARG_R_INT:
+ emit_mov(mrf, src_z);
+ break;
case SAMPLER_MESSAGE_ARG_SI_INT:
/* Note: on Gen7, this code may be reached with s_is_zero==true
* because in Gen7's ld2dss message, the sample index is the first
#undef S
#undef SWAP_XY_AND_XPYP
+static void
+brw_blorp_get_blit_kernel(struct brw_context *brw,
+ struct brw_blorp_params *params,
+ const struct brw_blorp_blit_prog_key *prog_key)
+{
+ if (brw_search_cache(&brw->cache, BRW_CACHE_BLORP_PROG,
+ prog_key, sizeof(*prog_key),
+ ¶ms->wm_prog_kernel, ¶ms->wm_prog_data))
+ return;
+
+ const unsigned *program;
+ unsigned program_size;
+ struct brw_blorp_prog_data prog_data;
+
+ /* Try and compile with NIR first. If that fails, fall back to the old
+ * method of building shaders manually.
+ */
+ nir_shader *nir = brw_blorp_build_nir_shader(brw, prog_key, &prog_data);
+ if (nir) {
+ struct brw_wm_prog_key wm_key;
+ brw_blorp_init_wm_prog_key(&wm_key);
+ wm_key.tex.compressed_multisample_layout_mask =
+ prog_key->tex_layout == INTEL_MSAA_LAYOUT_CMS;
+ wm_key.multisample_fbo = prog_key->rt_samples > 1;
+
+ program = brw_blorp_compile_nir_shader(brw, nir, &wm_key, false,
+ &prog_data, &program_size);
+ } else {
+ brw_blorp_blit_program prog(brw, prog_key);
+ program = prog.compile(brw, INTEL_DEBUG & DEBUG_BLORP, &program_size);
+ prog_data = prog.prog_data;
+ }
+
+ brw_upload_cache(&brw->cache, BRW_CACHE_BLORP_PROG,
+ prog_key, sizeof(*prog_key),
+ program, program_size,
+ &prog_data, sizeof(prog_data),
+ ¶ms->wm_prog_kernel, ¶ms->wm_prog_data);
+}
+
void
brw_blorp_blit_program::render_target_write()
{
/* Now write to the render target and terminate the thread */
emit_render_target_write(
mrf_rt_write,
- base_mrf,
+ brw->gen < 8 ? base_mrf : -1,
mrf_offset /* msg_length. TODO: Should be smaller for non-RGBA formats. */,
use_header);
}
-void
-brw_blorp_coord_transform_params::setup(GLfloat src0, GLfloat src1,
- GLfloat dst0, GLfloat dst1,
- bool mirror)
+static void
+brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform *xform,
+ GLfloat src0, GLfloat src1,
+ GLfloat dst0, GLfloat dst1,
+ bool mirror)
{
float scale = (src1 - src0) / (dst1 - dst0);
if (!mirror) {
* whereas the behaviour we actually want is "round to nearest",
* so 0.5 provides the necessary correction.
*/
- multiplier = scale;
- offset = src0 + (-dst0 + 0.5) * scale;
+ xform->multiplier = scale;
+ xform->offset = src0 + (-dst0 + 0.5f) * scale;
} else {
/* When mirroring X we need:
* src_x - src_x0 = dst_x1 - dst_x - 0.5
* Therefore:
* src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
*/
- multiplier = -scale;
- offset = src0 + (dst1 - 0.5) * scale;
+ xform->multiplier = -scale;
+ xform->offset = src0 + (dst1 - 0.5f) * scale;
}
}
intel_msaa_layout true_layout)
{
if (num_samples <= 1) {
+ /* Layout is used to determine if ld2dms is needed for sampling. In
+ * single sampled case normal ld is enough avoiding also the need to
+ * fetch mcs. Therefore simply set the layout to none.
+ */
+ if (brw->gen >= 9 && true_layout == INTEL_MSAA_LAYOUT_CMS) {
+ return INTEL_MSAA_LAYOUT_NONE;
+ }
+
/* When configuring the GPU for non-MSAA, we can still accommodate IMS
* format buffers, by transforming coordinates appropriately.
*/
}
-brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw,
- struct intel_mipmap_tree *src_mt,
- unsigned src_level, unsigned src_layer,
- mesa_format src_format,
- struct intel_mipmap_tree *dst_mt,
- unsigned dst_level, unsigned dst_layer,
- mesa_format dst_format,
- GLfloat src_x0, GLfloat src_y0,
- GLfloat src_x1, GLfloat src_y1,
- GLfloat dst_x0, GLfloat dst_y0,
- GLfloat dst_x1, GLfloat dst_y1,
- GLenum filter,
- bool mirror_x, bool mirror_y)
+/**
+ * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
+ * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
+ * the physical layer holding sample 0. So, for example, if
+ * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
+ * 4*n.
+ */
+void
+brw_blorp_blit_miptrees(struct brw_context *brw,
+ struct intel_mipmap_tree *src_mt,
+ unsigned src_level, unsigned src_layer,
+ mesa_format src_format, int src_swizzle,
+ struct intel_mipmap_tree *dst_mt,
+ unsigned dst_level, unsigned dst_layer,
+ mesa_format dst_format,
+ float src_x0, float src_y0,
+ float src_x1, float src_y1,
+ float dst_x0, float dst_y0,
+ float dst_x1, float dst_y1,
+ GLenum filter, bool mirror_x, bool mirror_y,
+ bool decode_srgb, bool encode_srgb)
{
- src.set(brw, src_mt, src_level, src_layer, src_format, false);
- dst.set(brw, dst_mt, dst_level, dst_layer, dst_format, true);
+ /* Get ready to blit. This includes depth resolving the src and dst
+ * buffers if necessary. Note: it's not necessary to do a color resolve on
+ * the destination buffer because we use the standard render path to render
+ * to destination color buffers, and the standard render path is
+ * fast-color-aware.
+ */
+ intel_miptree_resolve_color(brw, src_mt, INTEL_MIPTREE_IGNORE_CCS_E);
+ intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_layer);
+ intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_layer);
+
+ intel_miptree_prepare_mcs(brw, dst_mt);
+
+ DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
+ "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
+ __func__,
+ src_mt->num_samples, _mesa_get_format_name(src_mt->format), src_mt,
+ src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
+ dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt,
+ dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
+ mirror_x, mirror_y);
+
+ if (!decode_srgb && _mesa_get_format_color_encoding(src_format) == GL_SRGB)
+ src_format = _mesa_get_srgb_format_linear(src_format);
+
+ if (!encode_srgb && _mesa_get_format_color_encoding(dst_format) == GL_SRGB)
+ dst_format = _mesa_get_srgb_format_linear(dst_format);
+
+ struct brw_blorp_params params;
+ brw_blorp_params_init(¶ms);
+
+ brw_blorp_surface_info_init(brw, ¶ms.src, src_mt, src_level,
+ src_layer, src_format, false);
+ brw_blorp_surface_info_init(brw, ¶ms.dst, dst_mt, dst_level,
+ dst_layer, dst_format, true);
/* Even though we do multisample resolves at the time of the blit, OpenGL
* specification defines them as if they happen at the time of rendering,
* (aside from the color space), we choose to blit in sRGB space to get
* this higher quality image.
*/
- if (src.num_samples > 1 &&
+ if (params.src.num_samples > 1 &&
_mesa_get_format_color_encoding(dst_mt->format) == GL_SRGB &&
_mesa_get_srgb_format_linear(src_mt->format) ==
_mesa_get_srgb_format_linear(dst_mt->format)) {
assert(brw->format_supported_as_render_target[dst_mt->format]);
- dst.brw_surfaceformat = brw->render_target_format[dst_mt->format];
- src.brw_surfaceformat = brw_format_for_mesa_format(dst_mt->format);
+ params.dst.brw_surfaceformat = brw->render_target_format[dst_mt->format];
+ params.src.brw_surfaceformat = brw_format_for_mesa_format(dst_mt->format);
}
/* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
* shouldn't affect rendering correctness, since the destination format is
* R32_FLOAT, so only the contents of the red channel matters.
*/
- if (brw->gen == 6 && src.num_samples > 1 && dst.num_samples <= 1 &&
+ if (brw->gen == 6 &&
+ params.src.num_samples > 1 && params.dst.num_samples <= 1 &&
src_mt->format == dst_mt->format &&
- dst.brw_surfaceformat == BRW_SURFACEFORMAT_R32_FLOAT) {
- src.brw_surfaceformat = dst.brw_surfaceformat;
+ params.dst.brw_surfaceformat == BRW_SURFACEFORMAT_R32_FLOAT) {
+ params.src.brw_surfaceformat = params.dst.brw_surfaceformat;
}
- use_wm_prog = true;
+ struct brw_blorp_blit_prog_key wm_prog_key;
memset(&wm_prog_key, 0, sizeof(wm_prog_key));
/* texture_data_type indicates the register type that should be used to
* single-sampled texture and interleave the samples ourselves.
*/
if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS)
- dst.num_samples = 0;
+ params.dst.num_samples = 0;
}
- if (dst.map_stencil_as_y_tiled && dst.num_samples > 1) {
+ if (params.dst.map_stencil_as_y_tiled && params.dst.num_samples > 1) {
/* If the destination surface is a W-tiled multisampled stencil buffer
* that we're mapping as Y tiled, then we need to arrange for the WM
* program to run once per sample rather than once per pixel, because
wm_prog_key.persample_msaa_dispatch = true;
}
- if (src.num_samples > 0 && dst.num_samples > 1) {
+ if (params.src.num_samples > 0 && params.dst.num_samples > 1) {
/* We are blitting from a multisample buffer to a multisample buffer, so
* we must preserve samples within a pixel. This means we have to
* arrange for the WM program to run once per sample rather than once
/* Scaling factors used for bilinear filtering in multisample scaled
* blits.
*/
- wm_prog_key.x_scale = 2.0;
- wm_prog_key.y_scale = src_mt->num_samples / 2.0;
+ wm_prog_key.x_scale = 2.0f;
+ wm_prog_key.y_scale = src_mt->num_samples / 2.0f;
- if (filter == GL_LINEAR && src.num_samples <= 1 && dst.num_samples <= 1)
+ if (filter == GL_LINEAR &&
+ params.src.num_samples <= 1 && params.dst.num_samples <= 1)
wm_prog_key.bilinear_filter = true;
GLenum base_format = _mesa_get_format_base_format(src_mt->format);
if (base_format != GL_DEPTH_COMPONENT && /* TODO: what about depth/stencil? */
base_format != GL_STENCIL_INDEX &&
+ !_mesa_is_format_integer(src_mt->format) &&
src_mt->num_samples > 1 && dst_mt->num_samples <= 1) {
- /* We are downsampling a color buffer, so blend. */
+ /* We are downsampling a non-integer color buffer, so blend.
+ *
+ * Regarding integer color buffers, the OpenGL ES 3.2 spec says:
+ *
+ * "If the source formats are integer types or stencil values, a
+ * single sample's value is selected for each pixel."
+ *
+ * This implies we should not blend in that case.
+ */
wm_prog_key.blend = true;
}
/* tex_samples and rt_samples are the sample counts that are set up in
* SURFACE_STATE.
*/
- wm_prog_key.tex_samples = src.num_samples;
- wm_prog_key.rt_samples = dst.num_samples;
+ wm_prog_key.tex_samples = params.src.num_samples;
+ wm_prog_key.rt_samples = params.dst.num_samples;
/* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
* use to access the source and destination surfaces.
*/
wm_prog_key.tex_layout =
- compute_msaa_layout_for_pipeline(brw, src.num_samples, src.msaa_layout);
+ compute_msaa_layout_for_pipeline(brw, params.src.num_samples,
+ params.src.msaa_layout);
wm_prog_key.rt_layout =
- compute_msaa_layout_for_pipeline(brw, dst.num_samples, dst.msaa_layout);
+ compute_msaa_layout_for_pipeline(brw, params.dst.num_samples,
+ params.dst.msaa_layout);
/* src_layout and dst_layout indicate the true MSAA layout used by src and
* dst.
wm_prog_key.src_layout = src_mt->msaa_layout;
wm_prog_key.dst_layout = dst_mt->msaa_layout;
- wm_prog_key.src_tiled_w = src.map_stencil_as_y_tiled;
- wm_prog_key.dst_tiled_w = dst.map_stencil_as_y_tiled;
+ /* On gen9+ compressed single sampled buffers carry the same layout type as
+ * multisampled. The difference is that they can be sampled using normal
+ * ld message and as render target behave just like non-compressed surface
+ * from compiler point of view. Therefore override the type in the program
+ * key.
+ */
+ if (brw->gen >= 9 && params.src.num_samples <= 1 &&
+ src_mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS)
+ wm_prog_key.src_layout = INTEL_MSAA_LAYOUT_NONE;
+ if (brw->gen >= 9 && params.dst.num_samples <= 1 &&
+ dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS)
+ wm_prog_key.dst_layout = INTEL_MSAA_LAYOUT_NONE;
+
+ wm_prog_key.src_tiled_w = params.src.map_stencil_as_y_tiled;
+ wm_prog_key.dst_tiled_w = params.dst.map_stencil_as_y_tiled;
/* Round floating point values to nearest integer to avoid "off by one texel"
* kind of errors when blitting.
*/
- x0 = wm_push_consts.dst_x0 = roundf(dst_x0);
- y0 = wm_push_consts.dst_y0 = roundf(dst_y0);
- x1 = wm_push_consts.dst_x1 = roundf(dst_x1);
- y1 = wm_push_consts.dst_y1 = roundf(dst_y1);
- wm_push_consts.rect_grid_x1 = (minify(src_mt->logical_width0, src_level) *
- wm_prog_key.x_scale - 1.0);
- wm_push_consts.rect_grid_y1 = (minify(src_mt->logical_height0, src_level) *
- wm_prog_key.y_scale - 1.0);
-
- wm_push_consts.x_transform.setup(src_x0, src_x1, dst_x0, dst_x1, mirror_x);
- wm_push_consts.y_transform.setup(src_y0, src_y1, dst_y0, dst_y1, mirror_y);
-
- if (dst.num_samples <= 1 && dst_mt->num_samples > 1) {
+ params.x0 = params.wm_push_consts.dst_x0 = roundf(dst_x0);
+ params.y0 = params.wm_push_consts.dst_y0 = roundf(dst_y0);
+ params.x1 = params.wm_push_consts.dst_x1 = roundf(dst_x1);
+ params.y1 = params.wm_push_consts.dst_y1 = roundf(dst_y1);
+ params.wm_push_consts.rect_grid_x1 =
+ minify(src_mt->logical_width0, src_level) * wm_prog_key.x_scale - 1.0f;
+ params.wm_push_consts.rect_grid_y1 =
+ minify(src_mt->logical_height0, src_level) * wm_prog_key.y_scale - 1.0f;
+
+ brw_blorp_setup_coord_transform(¶ms.wm_push_consts.x_transform,
+ src_x0, src_x1, dst_x0, dst_x1, mirror_x);
+ brw_blorp_setup_coord_transform(¶ms.wm_push_consts.y_transform,
+ src_y0, src_y1, dst_y0, dst_y1, mirror_y);
+
+ params.wm_push_consts.src_z =
+ params.src.mt->target == GL_TEXTURE_3D ? params.src.layer : 0;
+
+ if (params.dst.num_samples <= 1 && dst_mt->num_samples > 1) {
/* We must expand the rectangle we send through the rendering pipeline,
* to account for the fact that we are mapping the destination region as
* single-sampled when it is in fact multisampled. We must also align
*/
assert(dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS);
switch (dst_mt->num_samples) {
+ case 2:
+ params.x0 = ROUND_DOWN_TO(params.x0 * 2, 4);
+ params.y0 = ROUND_DOWN_TO(params.y0, 4);
+ params.x1 = ALIGN(params.x1 * 2, 4);
+ params.y1 = ALIGN(params.y1, 4);
+ break;
case 4:
- x0 = ROUND_DOWN_TO(x0 * 2, 4);
- y0 = ROUND_DOWN_TO(y0 * 2, 4);
- x1 = ALIGN(x1 * 2, 4);
- y1 = ALIGN(y1 * 2, 4);
+ params.x0 = ROUND_DOWN_TO(params.x0 * 2, 4);
+ params.y0 = ROUND_DOWN_TO(params.y0 * 2, 4);
+ params.x1 = ALIGN(params.x1 * 2, 4);
+ params.y1 = ALIGN(params.y1 * 2, 4);
break;
case 8:
- x0 = ROUND_DOWN_TO(x0 * 4, 8);
- y0 = ROUND_DOWN_TO(y0 * 2, 4);
- x1 = ALIGN(x1 * 4, 8);
- y1 = ALIGN(y1 * 2, 4);
+ params.x0 = ROUND_DOWN_TO(params.x0 * 4, 8);
+ params.y0 = ROUND_DOWN_TO(params.y0 * 2, 4);
+ params.x1 = ALIGN(params.x1 * 4, 8);
+ params.y1 = ALIGN(params.y1 * 2, 4);
break;
default:
unreachable("Unrecognized sample count in brw_blorp_blit_params ctor");
wm_prog_key.use_kill = true;
}
- if (dst.map_stencil_as_y_tiled) {
+ if (params.dst.map_stencil_as_y_tiled) {
/* We must modify the rectangle we send through the rendering pipeline
* (and the size and x/y offset of the destination surface), to account
* for the fact that we are mapping it as Y-tiled when it is in fact
* TODO: what if this makes the coordinates (or the texture size) too
* large?
*/
- const unsigned x_align = 8, y_align = dst.num_samples != 0 ? 8 : 4;
- x0 = ROUND_DOWN_TO(x0, x_align) * 2;
- y0 = ROUND_DOWN_TO(y0, y_align) / 2;
- x1 = ALIGN(x1, x_align) * 2;
- y1 = ALIGN(y1, y_align) / 2;
- dst.width = ALIGN(dst.width, x_align) * 2;
- dst.height = ALIGN(dst.height, y_align) / 2;
- dst.x_offset *= 2;
- dst.y_offset /= 2;
+ const unsigned x_align = 8, y_align = params.dst.num_samples != 0 ? 8 : 4;
+ params.x0 = ROUND_DOWN_TO(params.x0, x_align) * 2;
+ params.y0 = ROUND_DOWN_TO(params.y0, y_align) / 2;
+ params.x1 = ALIGN(params.x1, x_align) * 2;
+ params.y1 = ALIGN(params.y1, y_align) / 2;
+ params.dst.width = ALIGN(params.dst.width, x_align) * 2;
+ params.dst.height = ALIGN(params.dst.height, y_align) / 2;
+ params.dst.x_offset *= 2;
+ params.dst.y_offset /= 2;
wm_prog_key.use_kill = true;
}
- if (src.map_stencil_as_y_tiled) {
+ if (params.src.map_stencil_as_y_tiled) {
/* We must modify the size and x/y offset of the source surface to
* account for the fact that we are mapping it as Y-tiled when it is in
* fact W tiled.
*
* TODO: what if this makes the texture size too large?
*/
- const unsigned x_align = 8, y_align = src.num_samples != 0 ? 8 : 4;
- src.width = ALIGN(src.width, x_align) * 2;
- src.height = ALIGN(src.height, y_align) / 2;
- src.x_offset *= 2;
- src.y_offset /= 2;
+ const unsigned x_align = 8, y_align = params.src.num_samples != 0 ? 8 : 4;
+ params.src.width = ALIGN(params.src.width, x_align) * 2;
+ params.src.height = ALIGN(params.src.height, y_align) / 2;
+ params.src.x_offset *= 2;
+ params.src.y_offset /= 2;
}
-}
-uint32_t
-brw_blorp_blit_params::get_wm_prog(struct brw_context *brw,
- brw_blorp_prog_data **prog_data) const
-{
- uint32_t prog_offset = 0;
- if (!brw_search_cache(&brw->cache, BRW_CACHE_BLORP_BLIT_PROG,
- &this->wm_prog_key, sizeof(this->wm_prog_key),
- &prog_offset, prog_data)) {
- brw_blorp_blit_program prog(brw, &this->wm_prog_key,
- INTEL_DEBUG & DEBUG_BLORP);
- GLuint program_size;
- const GLuint *program = prog.compile(brw, &program_size);
- brw_upload_cache(&brw->cache, BRW_CACHE_BLORP_BLIT_PROG,
- &this->wm_prog_key, sizeof(this->wm_prog_key),
- program, program_size,
- &prog.prog_data, sizeof(prog.prog_data),
- &prog_offset, prog_data);
- }
- return prog_offset;
+ brw_blorp_get_blit_kernel(brw, ¶ms, &wm_prog_key);
+
+ params.src.swizzle = src_swizzle;
+
+ brw_blorp_exec(brw, ¶ms);
+
+ intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_layer);
+
+ if (intel_miptree_is_lossless_compressed(brw, dst_mt))
+ dst_mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
}
projects / mesa.git / blobdiff