i965/vec4: Fix handling of multiple register reads and writes in split_virtual_grfs().

[mesa.git] / src / mesa / drivers / dri / i965 / brw_blorp_blit_eu.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
index 161c6798a578048e0691e76699e3f2e25ea04bdf..32919b13a62d22889e2e3b76b8c65335c0a6663a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
@@ -21,28 +21,20 @@
  * IN THE SOFTWARE.
  */
 
-#include "glsl/ralloc.h"
+#include "util/ralloc.h"
 #include "brw_blorp_blit_eu.h"
+#include "brw_blorp.h"
+#include "brw_cfg.h"
 
-brw_blorp_eu_emitter::brw_blorp_eu_emitter(struct brw_context *brw)
-   : mem_ctx(ralloc_context(NULL))
+brw_blorp_eu_emitter::brw_blorp_eu_emitter(struct brw_context *brw,
+                                           bool debug_flag)
+   : mem_ctx(ralloc_context(NULL)),
+     generator(brw, mem_ctx, (void *) rzalloc(mem_ctx, struct brw_wm_prog_key),
+               (struct brw_stage_prog_data *) rzalloc(mem_ctx, struct brw_wm_prog_data),
+               NULL, 0, false, "BLORP")
 {
-   brw_init_compile(brw, &func, mem_ctx);
-
-   /*
-    * By default everything is emitted as 16-wide with only a few expections
-    * handled explicitly either here in the compiler or by one of the specific
-    * code emission calls.
-    * It should be also noted that here in this file any alterations of the
-    * compression control settings are only used to affect the execution size
-    * of the instructions. The instruction template used to initialise all the
-    * instructions is effectively not altered -- the value stays at zero
-    * representing either GEN6_COMPRESSION_1Q or GEN6_COMPRESSION_1H depending
-    * on the context.
-    * If any other settings are used in the instruction headers, they are set
-    * elsewhere by the individual code emission calls.
-    */
-   brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
+   if (debug_flag)
+      generator.enable_debug("blorp");
 }
 
 brw_blorp_eu_emitter::~brw_blorp_eu_emitter()
@@ -51,17 +43,12 @@ brw_blorp_eu_emitter::~brw_blorp_eu_emitter()
 }
 
 const unsigned *
-brw_blorp_eu_emitter::get_program(unsigned *program_size, FILE *dump_file)
+brw_blorp_eu_emitter::get_program(unsigned *program_size)
 {
-   brw_set_uip_jip(&func);
+   cfg_t cfg(&insts);
+   generator.generate_code(&cfg, 16);
 
-   if (unlikely(INTEL_DEBUG & DEBUG_BLORP)) {
-      printf("Native code for BLORP blit:\n");
-      brw_dump_compile(&func, dump_file, 0, func.next_insn_offset);
-      printf("\n");
-   }
-
-   return brw_get_program(&func, program_size);
+   return generator.get_assembly(program_size);
 }
 
 /**
@@ -79,15 +66,70 @@ brw_blorp_eu_emitter::emit_kill_if_outside_rect(const struct brw_reg &x,
 {
    struct brw_reg f0 = brw_flag_reg(0, 0);
    struct brw_reg g1 = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
-   struct brw_reg null32 = vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 
-   brw_CMP(&func, null32, BRW_CONDITIONAL_GE, x, dst_x0);
-   brw_CMP(&func, null32, BRW_CONDITIONAL_GE, y, dst_y0);
-   brw_CMP(&func, null32, BRW_CONDITIONAL_L, x, dst_x1);
-   brw_CMP(&func, null32, BRW_CONDITIONAL_L, y, dst_y1);
+   emit_cmp(BRW_CONDITIONAL_GE, x, dst_x0);
+   emit_cmp(BRW_CONDITIONAL_GE, y, dst_y0)->predicate = BRW_PREDICATE_NORMAL;
+   emit_cmp(BRW_CONDITIONAL_L, x, dst_x1)->predicate = BRW_PREDICATE_NORMAL;
+   emit_cmp(BRW_CONDITIONAL_L, y, dst_y1)->predicate = BRW_PREDICATE_NORMAL;
+
+   fs_inst *inst = new (mem_ctx) fs_inst(BRW_OPCODE_AND, g1, f0, g1);
+   inst->force_writemask_all = true;
+   insts.push_tail(inst);
+}
+
+void
+brw_blorp_eu_emitter::emit_texture_lookup(const struct brw_reg &dst,
+                                          enum opcode op,
+                                          unsigned base_mrf,
+                                          unsigned msg_length)
+{
+   fs_inst *inst = new (mem_ctx) fs_inst(op, dst, brw_message_reg(base_mrf),
+                                         fs_reg(0u));
 
-   brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
+   inst->base_mrf = base_mrf;
+   inst->mlen = msg_length;
+   inst->header_present = false;
 
-   struct brw_instruction *inst = brw_AND(&func, g1, f0, g1);
-   inst->header.mask_control = BRW_MASK_DISABLE;
+   insts.push_tail(inst);
 }
+
+void
+brw_blorp_eu_emitter::emit_render_target_write(const struct brw_reg &src0,
+                                               unsigned msg_reg_nr,
+                                               unsigned msg_length,
+                                               bool use_header)
+{
+   fs_inst *inst = new (mem_ctx) fs_inst(FS_OPCODE_BLORP_FB_WRITE, 16);
+
+   inst->src[0] = src0;
+   inst->base_mrf = msg_reg_nr;
+   inst->mlen = msg_length;
+   inst->header_present = use_header;
+   inst->target = BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX;
+
+   insts.push_tail(inst);
+}
+
+void
+brw_blorp_eu_emitter::emit_combine(enum opcode combine_opcode,
+                                   const struct brw_reg &dst,
+                                   const struct brw_reg &src_1,
+                                   const struct brw_reg &src_2)
+{
+   assert(combine_opcode == BRW_OPCODE_ADD || combine_opcode == BRW_OPCODE_AVG);
+
+   insts.push_tail(new (mem_ctx) fs_inst(combine_opcode, dst, src_1, src_2));
+}
+
+fs_inst *
+brw_blorp_eu_emitter::emit_cmp(enum brw_conditional_mod op,
+                               const struct brw_reg &x,
+                               const struct brw_reg &y)
+{
+   fs_inst *cmp = new (mem_ctx) fs_inst(BRW_OPCODE_CMP,
+                                        vec16(brw_null_reg()), x, y);
+   cmp->conditional_mod = op;
+   insts.push_tail(cmp);
+   return cmp;
+}
+