i965/fs: Move some flags that affect code generation to fs_visitor.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_blorp_blit_eu.cpp
index 8d723d640520ad733236c4d6fea7245a3ba4747b..38969d8a920ad9fa1ee1933acd2cb23405107dbb 100644 (file)
 
 #include "glsl/ralloc.h"
 #include "brw_blorp_blit_eu.h"
+#include "brw_blorp.h"
 
 brw_blorp_eu_emitter::brw_blorp_eu_emitter(struct brw_context *brw)
-   : mem_ctx(ralloc_context(NULL))
+   : mem_ctx(ralloc_context(NULL)), c(rzalloc(mem_ctx, struct brw_wm_compile)),
+     generator(brw, c, NULL, NULL, false)
 {
-   brw_init_compile(brw, &func, mem_ctx);
-
-   /*
-    * By default everything is emitted as 16-wide with only a few expections
-    * handled explicitly either here in the compiler or by one of the specific
-    * code emission calls.
-    * It should be also noted that here in this file any alterations of the
-    * compression control settings are only used to affect the execution size
-    * of the instructions. The instruction template used to initialise all the
-    * instructions is effectively not altered -- the value stays at zero
-    * representing either GEN6_COMPRESSION_1Q or GEN6_COMPRESSION_1H depending
-    * on the context.
-    * If any other settings are used in the instruction headers, they are set
-    * elsewhere by the individual code emission calls.
-    */
-   brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
 }
 
 brw_blorp_eu_emitter::~brw_blorp_eu_emitter()
@@ -53,13 +39,98 @@ brw_blorp_eu_emitter::~brw_blorp_eu_emitter()
 const unsigned *
 brw_blorp_eu_emitter::get_program(unsigned *program_size, FILE *dump_file)
 {
-   brw_set_uip_jip(&func);
+   const unsigned *res;
 
    if (unlikely(INTEL_DEBUG & DEBUG_BLORP)) {
-      printf("Native code for BLORP blit:\n");
-      brw_dump_compile(&func, dump_file, 0, func.next_insn_offset);
-      printf("\n");
+      fprintf(stderr, "Native code for BLORP blit:\n");
+      res = generator.generate_assembly(NULL, &insts, program_size, dump_file);
+      fprintf(stderr, "\n");
+   } else {
+      res = generator.generate_assembly(NULL, &insts, program_size);
    }
 
-   return brw_get_program(&func, program_size);
+   return res;
 }
+
+/**
+ * Emit code that kills pixels whose X and Y coordinates are outside the
+ * boundary of the rectangle defined by the push constants (dst_x0, dst_y0,
+ * dst_x1, dst_y1).
+ */
+void
+brw_blorp_eu_emitter::emit_kill_if_outside_rect(const struct brw_reg &x,
+                                                const struct brw_reg &y,
+                                                const struct brw_reg &dst_x0,
+                                                const struct brw_reg &dst_x1,
+                                                const struct brw_reg &dst_y0,
+                                                const struct brw_reg &dst_y1)
+{
+   struct brw_reg f0 = brw_flag_reg(0, 0);
+   struct brw_reg g1 = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
+
+   emit_cmp(BRW_CONDITIONAL_GE, x, dst_x0);
+   emit_cmp(BRW_CONDITIONAL_GE, y, dst_y0)->predicate = BRW_PREDICATE_NORMAL;
+   emit_cmp(BRW_CONDITIONAL_L, x, dst_x1)->predicate = BRW_PREDICATE_NORMAL;
+   emit_cmp(BRW_CONDITIONAL_L, y, dst_y1)->predicate = BRW_PREDICATE_NORMAL;
+
+   fs_inst *inst = new (mem_ctx) fs_inst(BRW_OPCODE_AND, g1, f0, g1);
+   inst->force_writemask_all = true;
+   insts.push_tail(inst);
+}
+
+void
+brw_blorp_eu_emitter::emit_texture_lookup(const struct brw_reg &dst,
+                                          enum opcode op,
+                                          unsigned base_mrf,
+                                          unsigned msg_length)
+{
+   fs_inst *inst = new (mem_ctx) fs_inst(op, dst, brw_message_reg(base_mrf));
+
+   inst->base_mrf = base_mrf;
+   inst->mlen = msg_length;
+   inst->sampler = 0;
+   inst->header_present = false;
+
+   insts.push_tail(inst);
+}
+
+void
+brw_blorp_eu_emitter::emit_render_target_write(const struct brw_reg &src0,
+                                               unsigned msg_reg_nr,
+                                               unsigned msg_length,
+                                               bool use_header)
+{
+   fs_inst *inst = new (mem_ctx) fs_inst(FS_OPCODE_BLORP_FB_WRITE);
+
+   inst->src[0] = src0;
+   inst->base_mrf = msg_reg_nr;
+   inst->mlen = msg_length;
+   inst->header_present = use_header;
+   inst->target = BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX;
+
+   insts.push_tail(inst);
+}
+
+void
+brw_blorp_eu_emitter::emit_combine(enum opcode combine_opcode,
+                                   const struct brw_reg &dst,
+                                   const struct brw_reg &src_1,
+                                   const struct brw_reg &src_2)
+{
+   assert(combine_opcode == BRW_OPCODE_ADD || combine_opcode == BRW_OPCODE_AVG);
+
+   insts.push_tail(new (mem_ctx) fs_inst(combine_opcode, dst, src_1, src_2));
+}
+
+fs_inst *
+brw_blorp_eu_emitter::emit_cmp(int op,
+                               const struct brw_reg &x,
+                               const struct brw_reg &y)
+{
+   fs_inst *cmp = new (mem_ctx) fs_inst(BRW_OPCODE_CMP,
+                                        vec16(brw_null_reg()), x, y);
+   cmp->conditional_mod = op;
+   insts.push_tail(cmp);
+   return cmp;
+}
+