i965/nir/vec4: Prepare source and destination registers for ALU operations

[mesa.git] / src / mesa / drivers / dri / i965 / brw_blorp_blit_eu.h

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
index bfad4224a2cb67e49b927a3f38a18b84e769878d..8e44eb482c4e2af39eb64497dc040121affbe208 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.h
@@ -85,6 +85,15 @@ protected:
          new (mem_ctx) fs_inst(BRW_OPCODE_LRP, 16, dst, src1, src2, src3));
    }
 
+   inline void emit_mad(const struct brw_reg &dst,
+                        const struct brw_reg &src1,
+                        const struct brw_reg &src2,
+                        const struct brw_reg &src3)
+   {
+      insts.push_tail(
+         new (mem_ctx) fs_inst(BRW_OPCODE_MAD, 16, dst, src1, src2, src3));
+   }
+
    inline void emit_min(const struct brw_reg& dst,
                         const struct brw_reg& src1,
                         const struct brw_reg& src2)