virtual uint32_t get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const;
-protected:
brw_blorp_const_color_prog_key wm_prog_key;
};
*/
static bool
is_color_fast_clear_compatible(struct brw_context *brw,
- gl_format format,
+ mesa_format format,
const union gl_color_union *color)
{
if (_mesa_is_format_integer_color(format))
return false;
for (int i = 0; i < 4; i++) {
- if (color->f[i] != 0.0 && color->f[i] != 1.0) {
- perf_debug("Clear color unsupported by fast color clear. "
- "Falling back to slow clear.\n");
+ if (color->f[i] != 0.0 && color->f[i] != 1.0 &&
+ _mesa_format_has_color_component(format, i)) {
return false;
}
}
dst.set(brw, irb->mt, irb->mt_level, layer, true);
/* Override the surface format according to the context's sRGB rules. */
- gl_format format = _mesa_get_render_format(ctx, irb->mt->format);
+ mesa_format format = _mesa_get_render_format(ctx, irb->mt->format);
dst.brw_surfaceformat = brw->render_target_format[format];
x0 = fb->_Xmin;
* accessing tiled memory. Using this Message Type to access linear
* (untiled) memory is UNDEFINED."
*/
- if (irb->mt->region->tiling == I915_TILING_NONE)
+ if (irb->mt->tiling == I915_TILING_NONE)
wm_prog_key.use_simd16_replicated_data = false;
/* Constant color writes ignore everyting in blend and color calculator
* state. This is not documented.
*/
for (int i = 0; i < 4; i++) {
- if (!color_mask[i]) {
+ if (_mesa_format_has_color_component(irb->mt->format, i) &&
+ !color_mask[i]) {
color_write_disable[i] = true;
wm_prog_key.use_simd16_replicated_data = false;
}
* never larger than the size of a tile, so there is no danger of
* overflowing beyond the memory belonging to the region.
*/
- if (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE &&
- irb->mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_NO_MCS &&
+ if (irb->mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_NO_MCS &&
!partial_clear && wm_prog_key.use_simd16_replicated_data &&
is_color_fast_clear_compatible(brw, format, &ctx->Color.ClearColor)) {
memset(push_consts, 0xff, 4*sizeof(float));
*/
unsigned x_align, y_align, x_scaledown, y_scaledown;
- /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
- * Target(s)", beneath the "Fast Color Clear" bullet (p327):
- *
- * Clear pass must have a clear rectangle that must follow alignment
- * rules in terms of pixels and lines as shown in the table
- * below. Further, the clear-rectangle height and width must be
- * multiple of the following dimensions. If the height and width of
- * the render target being cleared do not meet these requirements,
- * an MCS buffer can be created such that it follows the requirement
- * and covers the RT.
- *
- * The alignment size in the table that follows is related to the
- * alignment size returned by intel_get_non_msrt_mcs_alignment(), but
- * with X alignment multiplied by 16 and Y alignment multiplied by 32.
- */
- intel_get_non_msrt_mcs_alignment(brw, irb->mt, &x_align, &y_align);
- x_align *= 16;
- y_align *= 32;
-
- /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
- * Target(s)", beneath the "Fast Color Clear" bullet (p327):
- *
- * In order to optimize the performance MCS buffer (when bound to 1X
- * RT) clear similarly to MCS buffer clear for MSRT case, clear rect
- * is required to be scaled by the following factors in the
- * horizontal and vertical directions:
- *
- * The X and Y scale down factors in the table that follows are each
- * equal to half the alignment value computed above.
- */
- x_scaledown = x_align / 2;
- y_scaledown = y_align / 2;
-
- /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
- * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
- * Clear of Non-MultiSampled Render Target Restrictions":
- *
- * Clear rectangle must be aligned to two times the number of pixels in
- * the table shown below due to 16x16 hashing across the slice.
- */
- x_align *= 2;
- y_align *= 2;
+ if (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE) {
+ /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
+ * Target(s)", beneath the "Fast Color Clear" bullet (p327):
+ *
+ * Clear pass must have a clear rectangle that must follow
+ * alignment rules in terms of pixels and lines as shown in the
+ * table below. Further, the clear-rectangle height and width
+ * must be multiple of the following dimensions. If the height
+ * and width of the render target being cleared do not meet these
+ * requirements, an MCS buffer can be created such that it
+ * follows the requirement and covers the RT.
+ *
+ * The alignment size in the table that follows is related to the
+ * alignment size returned by intel_get_non_msrt_mcs_alignment(), but
+ * with X alignment multiplied by 16 and Y alignment multiplied by 32.
+ */
+ intel_get_non_msrt_mcs_alignment(brw, irb->mt, &x_align, &y_align);
+ x_align *= 16;
+ y_align *= 32;
+
+ /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
+ * Target(s)", beneath the "Fast Color Clear" bullet (p327):
+ *
+ * In order to optimize the performance MCS buffer (when bound to
+ * 1X RT) clear similarly to MCS buffer clear for MSRT case,
+ * clear rect is required to be scaled by the following factors
+ * in the horizontal and vertical directions:
+ *
+ * The X and Y scale down factors in the table that follows are each
+ * equal to half the alignment value computed above.
+ */
+ x_scaledown = x_align / 2;
+ y_scaledown = y_align / 2;
+
+ /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
+ * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
+ * Clear of Non-MultiSampled Render Target Restrictions":
+ *
+ * Clear rectangle must be aligned to two times the number of
+ * pixels in the table shown below due to 16x16 hashing across the
+ * slice.
+ */
+ x_align *= 2;
+ y_align *= 2;
+ } else {
+ /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
+ * Target(s)", beneath the "MSAA Compression" bullet (p326):
+ *
+ * Clear pass for this case requires that scaled down primitive
+ * is sent down with upper left co-ordinate to coincide with
+ * actual rectangle being cleared. For MSAA, clear rectangle’s
+ * height and width need to as show in the following table in
+ * terms of (width,height) of the RT.
+ *
+ * MSAA Width of Clear Rect Height of Clear Rect
+ * 4X Ceil(1/8*width) Ceil(1/2*height)
+ * 8X Ceil(1/2*width) Ceil(1/2*height)
+ *
+ * The text "with upper left co-ordinate to coincide with actual
+ * rectangle being cleared" is a little confusing--it seems to imply
+ * that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
+ * feed the pipeline using the rectangle (x,y) to
+ * (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
+ * the number of samples. Experiments indicate that this is not
+ * quite correct; actually, what the hardware appears to do is to
+ * align whatever rectangle is sent down the pipeline to the nearest
+ * multiple of 2x2 blocks, and then scale it up by a factor of N
+ * horizontally and 2 vertically. So the resulting alignment is 4
+ * vertically and either 4 or 16 horizontally, and the scaledown
+ * factor is 2 vertically and either 2 or 8 horizontally.
+ */
+ switch (irb->mt->num_samples) {
+ case 4:
+ x_scaledown = 8;
+ break;
+ case 8:
+ x_scaledown = 2;
+ break;
+ default:
+ assert(!"Unexpected sample count for fast clear");
+ unreachable();
+ break;
+ }
+ y_scaledown = 2;
+ x_align = x_scaledown * 2;
+ y_align = y_scaledown * 2;
+ }
/* Do the alignment and scaledown. */
x0 = ROUND_DOWN_TO(x0, x_align) / x_scaledown;
alloc_regs();
- brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
+ brw_set_default_compression_control(&func, BRW_COMPRESSION_NONE);
struct brw_reg mrf_rt_write =
retype(vec16(brw_message_reg(base_mrf)), BRW_REGISTER_TYPE_F);
/* The message payload is a single register with the low 4 floats/ints
* filled with the constant clear color.
*/
- brw_set_mask_control(&func, BRW_MASK_DISABLE);
+ brw_set_default_mask_control(&func, BRW_MASK_DISABLE);
brw_MOV(&func, vec4(brw_message_reg(base_mrf)), clear_rgba);
- brw_set_mask_control(&func, BRW_MASK_ENABLE);
+ brw_set_default_mask_control(&func, BRW_MASK_ENABLE);
msg_type = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
mlen = 1;
/* The message payload is pairs of registers for 16 pixels each of r,
* g, b, and a.
*/
- brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
+ brw_set_default_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
brw_MOV(&func,
brw_message_reg(base_mrf + i * 2),
brw_vec1_grf(clear_rgba.nr, i));
- brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
+ brw_set_default_compression_control(&func, BRW_COMPRESSION_NONE);
}
msg_type = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
false /* header present */);
if (unlikely(INTEL_DEBUG & DEBUG_BLORP)) {
- printf("Native code for BLORP clear:\n");
- brw_dump_compile(&func, stdout, 0, func.next_insn_offset);
- printf("\n");
+ fprintf(stderr, "Native code for BLORP clear:\n");
+ brw_disassemble(brw, func.store, 0, func.next_insn_offset, stderr);
+ fprintf(stderr, "\n");
}
+
+ brw_compact_instructions(&func, 0, 0, NULL);
return brw_get_program(&func, program_size);
}
}
}
- DBG("%s to mt %p level %d layer %d\n", __FUNCTION__,
+ const char *clear_type;
+ if (is_fast_clear)
+ clear_type = "fast";
+ else if (params.wm_prog_key.use_simd16_replicated_data)
+ clear_type = "replicated";
+ else
+ clear_type = "slow";
+
+ DBG("%s (%s) to mt %p level %d layer %d\n", __FUNCTION__, clear_type,
irb->mt, irb->mt_level, irb->mt_layer);
brw_blorp_exec(brw, ¶ms);
extern "C" {
bool
brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,
- bool partial_clear)
+ GLbitfield mask, bool partial_clear)
{
for (unsigned buf = 0; buf < fb->_NumColorDrawBuffers; buf++) {
struct gl_renderbuffer *rb = fb->_ColorDrawBuffers[buf];
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
+ /* Only clear the buffers present in the provided mask */
+ if (((1 << fb->_ColorDrawBufferIndexes[buf]) & mask) == 0)
+ continue;
+
/* If this is an ES2 context or GL_ARB_ES2_compatibility is supported,
* the framebuffer can be complete with some attachments missing. In
* this case the _ColorDrawBuffers pointer will be NULL.
if (rb == NULL)
continue;
- if (fb->NumLayers > 0) {
+ if (fb->MaxNumLayers > 0) {
unsigned layer_multiplier =
(irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ?
irb->mt->num_samples : 1;
- assert(fb->NumLayers * layer_multiplier ==
- irb->mt->level[irb->mt_level].depth);
- for (unsigned layer = 0; layer < fb->NumLayers; layer++) {
+ unsigned num_layers = irb->layer_count;
+ for (unsigned layer = 0; layer < num_layers; layer++) {
if (!do_single_blorp_clear(brw, fb, rb, buf, partial_clear,
- layer * layer_multiplier)) {
+ irb->mt_layer + layer * layer_multiplier)) {
return false;
}
}
return false;
}
- intel_renderbuffer_set_needs_downsample(irb);
+ irb->need_downsample = true;
}
return true;
projects / mesa.git / blobdiff