i965/bufmgr: Add a BO_ALLOC_ZEROED flag

[mesa.git] / src / mesa / drivers / dri / i965 / brw_bufmgr.h

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index ec5eb4cd618ea27366172bf753a2c41d82051d5f..6a6051bb71ca1488d4833cac0347bd83391e166a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -114,7 +114,6 @@ struct brw_bo {
    void *map_gtt;
    /** WC CPU address for the buffer, saved across map/unmap cycles */
    void *map_wc;
-   int map_count;
 
    /** BO cache list */
    struct list_head head;
@@ -124,6 +123,11 @@ struct brw_bo {
     */
    bool reusable;
 
+   /**
+    * Boolean of whether this buffer has been shared with an external client.
+    */
+   bool external;
+
    /**
     * Boolean of whether this buffer is cache coherent
     */
@@ -131,6 +135,7 @@ struct brw_bo {
 };
 
 #define BO_ALLOC_FOR_RENDER (1<<0)
+#define BO_ALLOC_ZEROED     (1<<1)
 
 /**
  * Allocate a buffer object.
@@ -152,18 +157,36 @@ struct brw_bo *brw_bo_alloc(struct brw_bufmgr *bufmgr, const char *name,
  *  I915_TILING_NONE
  *  I915_TILING_X
  *  I915_TILING_Y
- *
- * Note the tiling format may be rejected; callers should check the
- * 'tiling_mode' field on return, as well as the pitch value, which
- * may have been rounded up to accommodate for tiling restrictions.
  */
 struct brw_bo *brw_bo_alloc_tiled(struct brw_bufmgr *bufmgr,
                                   const char *name,
-                                  int x, int y, int cpp,
+                                  uint64_t size,
                                   uint32_t tiling_mode,
-                                  uint32_t *pitch,
+                                  uint32_t pitch,
                                   unsigned flags);
 
+/**
+ * Allocate a tiled buffer object.
+ *
+ * Alignment for tiled objects is set automatically; the 'flags'
+ * argument provides a hint about how the object will be used initially.
+ *
+ * Valid tiling formats are:
+ *  I915_TILING_NONE
+ *  I915_TILING_X
+ *  I915_TILING_Y
+ *
+ * Note the tiling format may be rejected; callers should check the
+ * 'tiling_mode' field on return, as well as the pitch value, which
+ * may have been rounded up to accommodate for tiling restrictions.
+ */
+struct brw_bo *brw_bo_alloc_tiled_2d(struct brw_bufmgr *bufmgr,
+                                     const char *name,
+                                     int x, int y, int cpp,
+                                     uint32_t tiling_mode,
+                                     uint32_t *pitch,
+                                     unsigned flags);
+
 /** Takes a reference on a buffer object */
 void brw_bo_reference(struct brw_bo *bo);
 
@@ -195,14 +218,11 @@ MUST_CHECK void *brw_bo_map(struct brw_context *brw, struct brw_bo *bo, unsigned
  * Reduces the refcount on the userspace mapping of the buffer
  * object.
  */
-int brw_bo_unmap(struct brw_bo *bo);
+static inline int brw_bo_unmap(struct brw_bo *bo) { return 0; }
 
 /** Write data into an object. */
 int brw_bo_subdata(struct brw_bo *bo, uint64_t offset,
                    uint64_t size, const void *data);
-/** Read data from an object. */
-int brw_bo_get_subdata(struct brw_bo *bo, uint64_t offset,
-                       uint64_t size, void *data);
 /**
  * Waits for rendering to an object by the GPU to have completed.
  *
@@ -210,7 +230,7 @@ int brw_bo_get_subdata(struct brw_bo *bo, uint64_t offset,
  * bo_subdata, etc.  It is merely a way for the driver to implement
  * glFinish.
  */
-void brw_bo_wait_rendering(struct brw_context *brw, struct brw_bo *bo);
+void brw_bo_wait_rendering(struct brw_bo *bo);
 
 /**
  * Tears down the buffer manager instance.