i965: Fix execution size of scalar TCS barrier setup code.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_cc.c

diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index eeb63c6d0bd3b9e3ff6927d6fb009fc3ec25665c..2e8f0f79e3d09f57f78fb2608ec08dc6ff8abf5c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -45,26 +45,39 @@ brw_upload_cc_vp(struct brw_context *brw)
    struct brw_cc_viewport *ccv;
 
    ccv = brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
-                        sizeof(*ccv), 32, &brw->cc.vp_offset);
+                        sizeof(*ccv) * ctx->Const.MaxViewports, 32,
+                         &brw->cc.vp_offset);
 
    /* _NEW_TRANSFORM */
-   if (ctx->Transform.DepthClamp) {
-      /* _NEW_VIEWPORT */
-      ccv->min_depth = MIN2(ctx->ViewportArray[0].Near, ctx->ViewportArray[0].Far);
-      ccv->max_depth = MAX2(ctx->ViewportArray[0].Near, ctx->ViewportArray[0].Far);
-   } else {
-      ccv->min_depth = 0.0;
-      ccv->max_depth = 1.0;
+   for (unsigned i = 0; i < ctx->Const.MaxViewports; i++) {
+      if (ctx->Transform.DepthClamp) {
+         /* _NEW_VIEWPORT */
+         ccv[i].min_depth = MIN2(ctx->ViewportArray[i].Near,
+                                 ctx->ViewportArray[i].Far);
+         ccv[i].max_depth = MAX2(ctx->ViewportArray[i].Near,
+                                 ctx->ViewportArray[i].Far);
+      } else {
+         ccv[i].min_depth = 0.0;
+         ccv[i].max_depth = 1.0;
+      }
    }
 
-   brw->state.dirty.cache |= CACHE_NEW_CC_VP;
+   if (brw->gen >= 7) {
+      BEGIN_BATCH(2);
+      OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
+      OUT_BATCH(brw->cc.vp_offset);
+      ADVANCE_BATCH();
+   } else {
+      brw->ctx.NewDriverState |= BRW_NEW_CC_VP;
+   }
 }
 
 const struct brw_tracked_state brw_cc_vp = {
    .dirty = {
-      .mesa = _NEW_VIEWPORT | _NEW_TRANSFORM,
-      .brw = BRW_NEW_BATCH,
-      .cache = 0
+      .mesa = _NEW_TRANSFORM |
+              _NEW_VIEWPORT,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_BLORP,
    },
    .emit = brw_upload_cc_vp
 };
@@ -92,7 +105,7 @@ brw_fix_xRGB_alpha(GLenum function)
 }
 
 /**
- * Creates the state cache entry for the given CC unit key.
+ * Creates a CC unit packet from the current blend state.
  */
 static void upload_cc_unit(struct brw_context *brw)
 {
@@ -214,11 +227,11 @@ static void upload_cc_unit(struct brw_context *brw)
    if (brw->stats_wm || unlikely(INTEL_DEBUG & DEBUG_STATS))
       cc->cc5.statistics_enable = 1;
 
-   /* CACHE_NEW_CC_VP */
-   cc->cc4.cc_viewport_state_offset = (brw->batch.bo->offset +
+   /* BRW_NEW_CC_VP */
+   cc->cc4.cc_viewport_state_offset = (brw->batch.bo->offset64 +
                                       brw->cc.vp_offset) >> 5; /* reloc */
 
-   brw->state.dirty.cache |= CACHE_NEW_CC_UNIT;
+   brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
 
    /* Emit CC viewport relocation */
    drm_intel_bo_emit_reloc(brw->batch.bo,
@@ -230,9 +243,14 @@ static void upload_cc_unit(struct brw_context *brw)
 
 const struct brw_tracked_state brw_cc_unit = {
    .dirty = {
-      .mesa = _NEW_STENCIL | _NEW_COLOR | _NEW_DEPTH | _NEW_BUFFERS,
-      .brw = BRW_NEW_BATCH | BRW_NEW_STATS_WM,
-      .cache = CACHE_NEW_CC_VP
+      .mesa = _NEW_BUFFERS |
+              _NEW_COLOR |
+              _NEW_DEPTH |
+              _NEW_STENCIL,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_BLORP |
+             BRW_NEW_CC_VP |
+             BRW_NEW_STATS_WM,
    },
    .emit = upload_cc_unit,
 };
@@ -253,8 +271,8 @@ static void upload_blend_constant_color(struct brw_context *brw)
 const struct brw_tracked_state brw_blend_constant_color = {
    .dirty = {
       .mesa = _NEW_COLOR,
-      .brw = BRW_NEW_CONTEXT,
-      .cache = 0
+      .brw = BRW_NEW_CONTEXT |
+             BRW_NEW_BLORP,
    },
    .emit = upload_blend_constant_color
 };