i965/nir/vec4: Prepare source and destination registers for ALU operations

[mesa.git] / src / mesa / drivers / dri / i965 / brw_cc.c

diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index 2f4062b9b0fd0c1fbdd5da533e0ab22d3ca0e482..354c73321cd2c267cdfba2955de6f961d88d5849 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -62,14 +62,21 @@ brw_upload_cc_vp(struct brw_context *brw)
       }
    }
 
-   brw->state.dirty.cache |= CACHE_NEW_CC_VP;
+   if (brw->gen >= 7) {
+      BEGIN_BATCH(2);
+      OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
+      OUT_BATCH(brw->cc.vp_offset);
+      ADVANCE_BATCH();
+   } else {
+      brw->ctx.NewDriverState |= BRW_NEW_CC_VP;
+   }
 }
 
 const struct brw_tracked_state brw_cc_vp = {
    .dirty = {
-      .mesa = _NEW_VIEWPORT | _NEW_TRANSFORM,
+      .mesa = _NEW_TRANSFORM |
+              _NEW_VIEWPORT,
       .brw = BRW_NEW_BATCH,
-      .cache = 0
    },
    .emit = brw_upload_cc_vp
 };
@@ -97,7 +104,7 @@ brw_fix_xRGB_alpha(GLenum function)
 }
 
 /**
- * Creates the state cache entry for the given CC unit key.
+ * Creates a CC unit packet from the current blend state.
  */
 static void upload_cc_unit(struct brw_context *brw)
 {
@@ -219,11 +226,11 @@ static void upload_cc_unit(struct brw_context *brw)
    if (brw->stats_wm || unlikely(INTEL_DEBUG & DEBUG_STATS))
       cc->cc5.statistics_enable = 1;
 
-   /* CACHE_NEW_CC_VP */
+   /* BRW_NEW_CC_VP */
    cc->cc4.cc_viewport_state_offset = (brw->batch.bo->offset64 +
                                       brw->cc.vp_offset) >> 5; /* reloc */
 
-   brw->state.dirty.cache |= CACHE_NEW_CC_UNIT;
+   brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
 
    /* Emit CC viewport relocation */
    drm_intel_bo_emit_reloc(brw->batch.bo,
@@ -235,9 +242,13 @@ static void upload_cc_unit(struct brw_context *brw)
 
 const struct brw_tracked_state brw_cc_unit = {
    .dirty = {
-      .mesa = _NEW_STENCIL | _NEW_COLOR | _NEW_DEPTH | _NEW_BUFFERS,
-      .brw = BRW_NEW_BATCH | BRW_NEW_STATS_WM,
-      .cache = CACHE_NEW_CC_VP
+      .mesa = _NEW_BUFFERS |
+              _NEW_COLOR |
+              _NEW_DEPTH |
+              _NEW_STENCIL,
+      .brw = BRW_NEW_BATCH |
+             BRW_NEW_CC_VP |
+             BRW_NEW_STATS_WM,
    },
    .emit = upload_cc_unit,
 };
@@ -259,7 +270,6 @@ const struct brw_tracked_state brw_blend_constant_color = {
    .dirty = {
       .mesa = _NEW_COLOR,
       .brw = BRW_NEW_CONTEXT,
-      .cache = 0
    },
    .emit = upload_blend_constant_color
 };