i965/fs: Lower 32x32 bit multiplication on BXT.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_cc.c

diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index 86ab503e2e2ef165c1dfae987706d90331819871..354c73321cd2c267cdfba2955de6f961d88d5849 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -68,7 +68,7 @@ brw_upload_cc_vp(struct brw_context *brw)
       OUT_BATCH(brw->cc.vp_offset);
       ADVANCE_BATCH();
    } else {
-      brw->state.dirty.cache |= CACHE_NEW_CC_VP;
+      brw->ctx.NewDriverState |= BRW_NEW_CC_VP;
    }
 }
 
@@ -77,7 +77,6 @@ const struct brw_tracked_state brw_cc_vp = {
       .mesa = _NEW_TRANSFORM |
               _NEW_VIEWPORT,
       .brw = BRW_NEW_BATCH,
-      .cache = 0
    },
    .emit = brw_upload_cc_vp
 };
@@ -227,11 +226,11 @@ static void upload_cc_unit(struct brw_context *brw)
    if (brw->stats_wm || unlikely(INTEL_DEBUG & DEBUG_STATS))
       cc->cc5.statistics_enable = 1;
 
-   /* CACHE_NEW_CC_VP */
+   /* BRW_NEW_CC_VP */
    cc->cc4.cc_viewport_state_offset = (brw->batch.bo->offset64 +
                                       brw->cc.vp_offset) >> 5; /* reloc */
 
-   brw->state.dirty.brw |= BRW_NEW_GEN4_UNIT_STATE;
+   brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
 
    /* Emit CC viewport relocation */
    drm_intel_bo_emit_reloc(brw->batch.bo,
@@ -248,8 +247,8 @@ const struct brw_tracked_state brw_cc_unit = {
               _NEW_DEPTH |
               _NEW_STENCIL,
       .brw = BRW_NEW_BATCH |
+             BRW_NEW_CC_VP |
              BRW_NEW_STATS_WM,
-      .cache = CACHE_NEW_CC_VP
    },
    .emit = upload_cc_unit,
 };
@@ -271,7 +270,6 @@ const struct brw_tracked_state brw_blend_constant_color = {
    .dirty = {
       .mesa = _NEW_COLOR,
       .brw = BRW_NEW_CONTEXT,
-      .cache = 0
    },
    .emit = upload_blend_constant_color
 };