i965/fs: Add support for translating ir_triop_fma into MAD.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_cc.c

diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index 988b85e73c95c3d0ade8cd6dbd67c48e4bcc17c7..6f85f6355cbd7dc25d62c30759dbec944afe0010 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -35,12 +35,13 @@
 #include "brw_defines.h"
 #include "brw_util.h"
 #include "main/macros.h"
+#include "main/stencil.h"
 #include "intel_batchbuffer.h"
 
 static void
 brw_upload_cc_vp(struct brw_context *brw)
 {
-   struct gl_context *ctx = &brw->intel.ctx;
+   struct gl_context *ctx = &brw->ctx;
    struct brw_cc_viewport *ccv;
 
    ccv = brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
@@ -95,15 +96,14 @@ brw_fix_xRGB_alpha(GLenum function)
  */
 static void upload_cc_unit(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &brw->intel.ctx;
+   struct gl_context *ctx = &brw->ctx;
    struct brw_cc_unit_state *cc;
 
    cc = brw_state_batch(brw, AUB_TRACE_CC_STATE,
                        sizeof(*cc), 64, &brw->cc.state_offset);
    memset(cc, 0, sizeof(*cc));
 
-   /* _NEW_STENCIL */
+   /* _NEW_STENCIL | _NEW_BUFFERS */
    if (ctx->Stencil._Enabled) {
       const unsigned back = ctx->Stencil._BackFace;
 
@@ -116,7 +116,7 @@ static void upload_cc_unit(struct brw_context *brw)
         intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]);
       cc->cc0.stencil_pass_depth_pass_op =
         intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]);
-      cc->cc1.stencil_ref = ctx->Stencil.Ref[0];
+      cc->cc1.stencil_ref = _mesa_get_stencil_ref(ctx, 0);
       cc->cc1.stencil_write_mask = ctx->Stencil.WriteMask[0];
       cc->cc1.stencil_test_mask = ctx->Stencil.ValueMask[0];
 
@@ -130,7 +130,7 @@ static void upload_cc_unit(struct brw_context *brw)
            intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]);
         cc->cc0.bf_stencil_pass_depth_pass_op =
            intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]);
-        cc->cc1.bf_stencil_ref = ctx->Stencil.Ref[back];
+        cc->cc1.bf_stencil_ref = _mesa_get_stencil_ref(ctx, back);
         cc->cc2.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
         cc->cc2.bf_stencil_test_mask = ctx->Stencil.ValueMask[back];
       }
@@ -210,26 +210,26 @@ static void upload_cc_unit(struct brw_context *brw)
       cc->cc2.depth_write_enable = ctx->Depth.Mask;
    }
 
-   if (intel->stats_wm || unlikely(INTEL_DEBUG & DEBUG_STATS))
+   if (brw->stats_wm || unlikely(INTEL_DEBUG & DEBUG_STATS))
       cc->cc5.statistics_enable = 1;
 
    /* CACHE_NEW_CC_VP */
-   cc->cc4.cc_viewport_state_offset = (intel->batch.bo->offset +
+   cc->cc4.cc_viewport_state_offset = (brw->batch.bo->offset +
                                       brw->cc.vp_offset) >> 5; /* reloc */
 
    brw->state.dirty.cache |= CACHE_NEW_CC_UNIT;
 
    /* Emit CC viewport relocation */
-   drm_intel_bo_emit_reloc(brw->intel.batch.bo,
+   drm_intel_bo_emit_reloc(brw->batch.bo,
                           (brw->cc.state_offset +
                            offsetof(struct brw_cc_unit_state, cc4)),
-                          intel->batch.bo, brw->cc.vp_offset,
+                          brw->batch.bo, brw->cc.vp_offset,
                           I915_GEM_DOMAIN_INSTRUCTION, 0);
 }
 
 const struct brw_tracked_state brw_cc_unit = {
    .dirty = {
-      .mesa = _NEW_STENCIL | _NEW_COLOR | _NEW_DEPTH,
+      .mesa = _NEW_STENCIL | _NEW_COLOR | _NEW_DEPTH | _NEW_BUFFERS,
       .brw = BRW_NEW_BATCH | BRW_NEW_STATS_WM,
       .cache = CACHE_NEW_CC_VP
    },
@@ -238,8 +238,7 @@ const struct brw_tracked_state brw_cc_unit = {
 
 static void upload_blend_constant_color(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &intel->ctx;
+   struct gl_context *ctx = &brw->ctx;
 
    BEGIN_BATCH(5);
    OUT_BATCH(_3DSTATE_BLEND_CONSTANT_COLOR << 16 | (5-2));