#include "brw_defines.h"
#include "brw_util.h"
#include "main/macros.h"
+#include "main/stencil.h"
#include "intel_batchbuffer.h"
static void
brw_upload_cc_vp(struct brw_context *brw)
{
- struct gl_context *ctx = &brw->intel.ctx;
+ struct gl_context *ctx = &brw->ctx;
struct brw_cc_viewport *ccv;
ccv = brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
* replace it with a function that hard-wires destination alpha to 1.0. This
* is used when rendering to xRGB targets.
*/
-static GLenum
-fix_xRGB_alpha(GLenum function)
+GLenum
+brw_fix_xRGB_alpha(GLenum function)
{
switch (function) {
case GL_DST_ALPHA:
*/
static void upload_cc_unit(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &brw->intel.ctx;
+ struct gl_context *ctx = &brw->ctx;
struct brw_cc_unit_state *cc;
cc = brw_state_batch(brw, AUB_TRACE_CC_STATE,
sizeof(*cc), 64, &brw->cc.state_offset);
memset(cc, 0, sizeof(*cc));
- /* _NEW_STENCIL */
+ /* _NEW_STENCIL | _NEW_BUFFERS */
if (ctx->Stencil._Enabled) {
const unsigned back = ctx->Stencil._BackFace;
intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]);
cc->cc0.stencil_pass_depth_pass_op =
intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]);
- cc->cc1.stencil_ref = ctx->Stencil.Ref[0];
+ cc->cc1.stencil_ref = _mesa_get_stencil_ref(ctx, 0);
cc->cc1.stencil_write_mask = ctx->Stencil.WriteMask[0];
cc->cc1.stencil_test_mask = ctx->Stencil.ValueMask[0];
intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]);
cc->cc0.bf_stencil_pass_depth_pass_op =
intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]);
- cc->cc1.bf_stencil_ref = ctx->Stencil.Ref[back];
+ cc->cc1.bf_stencil_ref = _mesa_get_stencil_ref(ctx, back);
cc->cc2.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
cc->cc2.bf_stencil_test_mask = ctx->Stencil.ValueMask[back];
}
* with GL_ONE and GL_ONE_MINUS_DST_ALPHA with GL_ZERO.
*/
if (ctx->DrawBuffer->Visual.alphaBits == 0) {
- srcRGB = fix_xRGB_alpha(srcRGB);
- srcA = fix_xRGB_alpha(srcA);
- dstRGB = fix_xRGB_alpha(dstRGB);
- dstA = fix_xRGB_alpha(dstA);
+ srcRGB = brw_fix_xRGB_alpha(srcRGB);
+ srcA = brw_fix_xRGB_alpha(srcA);
+ dstRGB = brw_fix_xRGB_alpha(dstRGB);
+ dstA = brw_fix_xRGB_alpha(dstA);
}
if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
cc->cc2.depth_write_enable = ctx->Depth.Mask;
}
- if (intel->stats_wm || unlikely(INTEL_DEBUG & DEBUG_STATS))
+ if (brw->stats_wm || unlikely(INTEL_DEBUG & DEBUG_STATS))
cc->cc5.statistics_enable = 1;
/* CACHE_NEW_CC_VP */
- cc->cc4.cc_viewport_state_offset = (intel->batch.bo->offset +
+ cc->cc4.cc_viewport_state_offset = (brw->batch.bo->offset +
brw->cc.vp_offset) >> 5; /* reloc */
brw->state.dirty.cache |= CACHE_NEW_CC_UNIT;
/* Emit CC viewport relocation */
- drm_intel_bo_emit_reloc(brw->intel.batch.bo,
+ drm_intel_bo_emit_reloc(brw->batch.bo,
(brw->cc.state_offset +
offsetof(struct brw_cc_unit_state, cc4)),
- intel->batch.bo, brw->cc.vp_offset,
+ brw->batch.bo, brw->cc.vp_offset,
I915_GEM_DOMAIN_INSTRUCTION, 0);
}
const struct brw_tracked_state brw_cc_unit = {
.dirty = {
- .mesa = _NEW_STENCIL | _NEW_COLOR | _NEW_DEPTH,
- .brw = BRW_NEW_BATCH,
+ .mesa = _NEW_STENCIL | _NEW_COLOR | _NEW_DEPTH | _NEW_BUFFERS,
+ .brw = BRW_NEW_BATCH | BRW_NEW_STATS_WM,
.cache = CACHE_NEW_CC_VP
},
.emit = upload_cc_unit,
static void upload_blend_constant_color(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
- struct gl_context *ctx = &intel->ctx;
+ struct gl_context *ctx = &brw->ctx;
BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_BLEND_CONSTANT_COLOR << 16 | (5-2));