i965/vec4: Don't lose the force_writemask_all flag during CSE.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_clear.c

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index d94e25976628a5895a5c5ed232f08bd49c70b030..12314204803064b0612080dc0e1d0183731a23bd 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -1,6 +1,6 @@
 /**************************************************************************
  *
- * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * Copyright 2003 VMware, Inc.
  * Copyright 2009, 2012 Intel Corporation.
  * All Rights Reserved.
  *
@@ -19,7 +19,7 @@
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -36,7 +36,6 @@
 #include "intel_blit.h"
 #include "intel_fbo.h"
 #include "intel_mipmap_tree.h"
-#include "intel_regions.h"
 
 #include "brw_context.h"
 #include "brw_blorp.h"
@@ -83,10 +82,10 @@ debug_mask(const char *name, GLbitfield mask)
 static bool
 noop_scissor(struct gl_context *ctx, struct gl_framebuffer *fb)
 {
-   return ctx->Scissor.X <= 0 &&
-          ctx->Scissor.Y <= 0 &&
-          ctx->Scissor.Width >= fb->Width &&
-          ctx->Scissor.Height >= fb->Height;
+   return ctx->Scissor.ScissorArray[0].X <= 0 &&
+          ctx->Scissor.ScissorArray[0].Y <= 0 &&
+          ctx->Scissor.ScissorArray[0].Width >= fb->Width &&
+          ctx->Scissor.ScissorArray[0].Height >= fb->Height;
 }
 
 /**
@@ -111,7 +110,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
    struct intel_mipmap_tree *mt = depth_irb->mt;
    struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH];
 
-   if (brw->gen < 6 || brw->gen >= 8)
+   if (brw->gen < 6)
       return false;
 
    if (!intel_renderbuffer_has_hiz(depth_irb))
@@ -121,7 +120,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
     * a previous clear had happened at a different clear value and resolve it
     * first.
     */
-   if (ctx->Scissor.Enabled && !noop_scissor(ctx, fb)) {
+   if ((ctx->Scissor.EnableFlags & 1) && !noop_scissor(ctx, fb)) {
       perf_debug("Failed to fast clear depth due to scissor being enabled.  "
                  "Possible 5%% performance win if avoided.\n");
       return false;
@@ -129,8 +128,8 @@ brw_fast_clear_depth(struct gl_context *ctx)
 
    uint32_t depth_clear_value;
    switch (mt->format) {
-   case MESA_FORMAT_Z32_FLOAT_X24S8:
-   case MESA_FORMAT_S8_Z24:
+   case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
+   case MESA_FORMAT_Z24_UNORM_S8_UINT:
       /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
        *
        *     "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
@@ -141,11 +140,11 @@ brw_fast_clear_depth(struct gl_context *ctx)
        */
       return false;
 
-   case MESA_FORMAT_Z32_FLOAT:
+   case MESA_FORMAT_Z_FLOAT32:
       depth_clear_value = float_as_int(ctx->Depth.Clear);
       break;
 
-   case MESA_FORMAT_Z16:
+   case MESA_FORMAT_Z_UNORM16:
       /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
        *
        *     "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
@@ -155,12 +154,17 @@ brw_fast_clear_depth(struct gl_context *ctx)
        *        width of the map (LOD0) is not multiple of 16, fast clear
        *        optimization must be disabled.
        */
-      if (brw->gen == 6 && (mt->level[depth_irb->mt_level].width % 16) != 0)
+      if (brw->gen == 6 &&
+          (minify(mt->physical_width0,
+                  depth_irb->mt_level - mt->first_level) % 16) != 0)
         return false;
       /* FALLTHROUGH */
 
    default:
-      depth_clear_value = fb->_DepthMax * ctx->Depth.Clear;
+      if (brw->gen >= 8)
+         depth_clear_value = float_as_int(ctx->Depth.Clear);
+      else
+         depth_clear_value = fb->_DepthMax * ctx->Depth.Clear;
       break;
    }
 
@@ -181,8 +185,16 @@ brw_fast_clear_depth(struct gl_context *ctx)
     */
    intel_batchbuffer_emit_mi_flush(brw);
 
-   intel_hiz_exec(brw, mt, depth_irb->mt_level, depth_irb->mt_layer,
-                 GEN6_HIZ_OP_DEPTH_CLEAR);
+   if (fb->MaxNumLayers > 0) {
+      for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) {
+         intel_hiz_exec(brw, mt, depth_irb->mt_level,
+                        depth_irb->mt_layer + layer,
+                        GEN6_HIZ_OP_DEPTH_CLEAR);
+      }
+   } else {
+      intel_hiz_exec(brw, mt, depth_irb->mt_level, depth_irb->mt_layer,
+                     GEN6_HIZ_OP_DEPTH_CLEAR);
+   }
 
    if (brw->gen == 6) {
       /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
@@ -210,7 +222,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
 {
    struct brw_context *brw = brw_context(ctx);
    struct gl_framebuffer *fb = ctx->DrawBuffer;
-   bool partial_clear = ctx->Scissor.Enabled && !noop_scissor(ctx, fb);
+   bool partial_clear = ctx->Scissor.EnableFlags && !noop_scissor(ctx, fb);
 
    if (!_mesa_check_conditional_render(ctx))
       return;
@@ -229,13 +241,11 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
       }
    }
 
-   /* BLORP is currently only supported on Gen6+. */
-   if (brw->gen >= 6 && brw->gen < 8) {
-      if (mask & BUFFER_BITS_COLOR) {
-         if (brw_blorp_clear_color(brw, fb, partial_clear)) {
-            debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
-            mask &= ~BUFFER_BITS_COLOR;
-         }
+   /* Clear color buffers with fast clear or at least rep16 writes. */
+   if (brw->gen >= 6 && brw->gen < 9 && (mask & BUFFER_BITS_COLOR)) {
+      if (brw_meta_fast_clear(brw, fb, mask, partial_clear)) {
+         debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
+         mask &= ~BUFFER_BITS_COLOR;
       }
    }