i915: Remove most of the code under gen >= 4 checks.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_clear.c

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index 31c2e45bd0caef07e3eceece5515005e743aa9cd..80b7a0c0751c2ef143c73b7f3eb9045660a4e3bf 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -40,6 +40,9 @@
 #include "intel_mipmap_tree.h"
 #include "intel_regions.h"
 
+#include "brw_context.h"
+#include "brw_blorp.h"
+
 #define FILE_DEBUG_FLAG DEBUG_BLIT
 
 static const char *buffer_names[] = {
@@ -76,6 +79,18 @@ debug_mask(const char *name, GLbitfield mask)
    }
 }
 
+/**
+ * Returns true if the scissor is a noop (cuts out nothing).
+ */
+static bool
+noop_scissor(struct gl_context *ctx, struct gl_framebuffer *fb)
+{
+   return ctx->Scissor.X <= 0 &&
+          ctx->Scissor.Y <= 0 &&
+          ctx->Scissor.Width >= fb->Width &&
+          ctx->Scissor.Height >= fb->Height;
+}
+
 /**
  * Implements fast depth clears on gen6+.
  *
@@ -100,21 +115,16 @@ brw_fast_clear_depth(struct gl_context *ctx)
    if (intel->gen < 6)
       return false;
 
-   if (!mt->hiz_mt)
+   if (!intel_renderbuffer_has_hiz(depth_irb))
       return false;
 
    /* We only handle full buffer clears -- otherwise you'd have to track whether
     * a previous clear had happened at a different clear value and resolve it
     * first.
     */
-   if (ctx->Scissor.Enabled)
-      return false;
-
-   /* The rendered area has to be 8x4 samples, not resolved pixels, so we look
-    * at the miptree slice dimensions instead of renderbuffer size.
-    */
-   if (mt->level[depth_irb->mt_level].width % 8 != 0 ||
-       mt->level[depth_irb->mt_level].height % 4 != 0) {
+   if (ctx->Scissor.Enabled && !noop_scissor(ctx, fb)) {
+      perf_debug("Failed to fast clear depth due to scissor being enabled.  "
+                 "Possible 5%% performance win if avoided.\n");
       return false;
    }
 
@@ -185,11 +195,9 @@ brw_fast_clear_depth(struct gl_context *ctx)
       intel_batchbuffer_emit_mi_flush(intel);
    }
 
-   /* Now, the entire HiZ buffer contains data that needs to be resolved to the
-    * entire depth buffer (so any previous resolve records should get tossed
-    * out).
+   /* Now, the HiZ buffer contains data that needs to be resolved to the depth
+    * buffer.
     */
-   intel_resolve_map_clear(&mt->hiz_map);
    intel_renderbuffer_set_needs_depth_resolve(depth_irb);
 
    return true;
@@ -201,7 +209,10 @@ brw_fast_clear_depth(struct gl_context *ctx)
 static void
 brw_clear(struct gl_context *ctx, GLbitfield mask)
 {
-   struct intel_context *intel = intel_context(ctx);
+   struct brw_context *brw = brw_context(ctx);
+   struct intel_context *intel = &brw->intel;
+   struct gl_framebuffer *fb = ctx->DrawBuffer;
+   bool partial_clear = ctx->Scissor.Enabled && !noop_scissor(ctx, fb);
 
    if (!_mesa_check_conditional_render(ctx))
       return;
@@ -211,6 +222,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
    }
 
    intel_prepare_render(intel);
+   brw_workaround_depthstencil_alignment(brw, partial_clear ? 0 : mask);
 
    if (mask & BUFFER_BIT_DEPTH) {
       if (brw_fast_clear_depth(ctx)) {
@@ -219,6 +231,16 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
       }
    }
 
+   /* BLORP is currently only supported on Gen6+. */
+   if (intel->gen >= 6) {
+      if (mask & BUFFER_BITS_COLOR) {
+         if (brw_blorp_clear_color(intel, fb, partial_clear)) {
+            debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
+            mask &= ~BUFFER_BITS_COLOR;
+         }
+      }
+   }
+
    GLbitfield tri_mask = mask & (BUFFER_BITS_COLOR |
                                 BUFFER_BIT_STENCIL |
                                 BUFFER_BIT_DEPTH);
@@ -226,7 +248,12 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
    if (tri_mask) {
       debug_mask("tri", tri_mask);
       mask &= ~tri_mask;
-      _mesa_meta_glsl_Clear(&intel->ctx, tri_mask);
+
+      if (ctx->API == API_OPENGLES) {
+         _mesa_meta_Clear(&intel->ctx, tri_mask);
+      } else {
+         _mesa_meta_glsl_Clear(&intel->ctx, tri_mask);
+      }
    }
 
    /* Any strange buffers get passed off to swrast */