-/**************************************************************************
- *
- * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
- * Copyright 2009 Intel Corporation.
+/*
+ * Copyright 2003 VMware, Inc.
+ * Copyright 2009, 2012 Intel Corporation.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
+ * distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
+ */
-#include "main/glheader.h"
#include "main/mtypes.h"
#include "main/condrender.h"
#include "swrast/swrast.h"
#include "drivers/common/meta.h"
-#include "intel_context.h"
-#include "intel_blit.h"
-#include "intel_clear.h"
+#include "intel_batchbuffer.h"
#include "intel_fbo.h"
-#include "intel_regions.h"
+#include "intel_mipmap_tree.h"
+
+#include "brw_context.h"
+#include "brw_blorp.h"
+#include "brw_defines.h"
#define FILE_DEBUG_FLAG DEBUG_BLIT
}
/**
- * Called by ctx->Driver.Clear.
+ * Returns true if the scissor is a noop (cuts out nothing).
*/
-static void
-intelClear(struct gl_context *ctx, GLbitfield mask)
+static bool
+noop_scissor(struct gl_framebuffer *fb)
{
- struct intel_context *intel = intel_context(ctx);
- const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask[0]);
- GLbitfield tri_mask = 0;
- GLbitfield blit_mask = 0;
- GLbitfield swrast_mask = 0;
+ return fb->_Xmin <= 0 &&
+ fb->_Ymin <= 0 &&
+ fb->_Xmax >= fb->Width &&
+ fb->_Ymax >= fb->Height;
+}
+
+/**
+ * Implements fast depth clears on gen6+.
+ *
+ * Fast clears basically work by setting a flag in each of the subspans
+ * represented in the HiZ buffer that says "When you need the depth values for
+ * this subspan, it's the hardware's current clear value." Then later rendering
+ * can just use the static clear value instead of referencing memory.
+ *
+ * The tricky part of the implementation is that you have to have the clear
+ * value that was used on the depth buffer in place for all further rendering,
+ * at least until a resolve to the real depth buffer happens.
+ */
+static bool
+brw_fast_clear_depth(struct gl_context *ctx)
+{
+ struct brw_context *brw = brw_context(ctx);
struct gl_framebuffer *fb = ctx->DrawBuffer;
- struct intel_renderbuffer *irb;
- int i;
+ struct intel_renderbuffer *depth_irb =
+ intel_get_renderbuffer(fb, BUFFER_DEPTH);
+ struct intel_mipmap_tree *mt = depth_irb->mt;
+ struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH];
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
- if (!_mesa_check_conditional_render(ctx))
- return;
+ if (INTEL_DEBUG & DEBUG_NO_FAST_CLEAR)
+ return false;
- if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
- intel->front_buffer_dirty = true;
+ if (devinfo->gen < 6)
+ return false;
+
+ if (!intel_renderbuffer_has_hiz(depth_irb))
+ return false;
+
+ /* We only handle full buffer clears -- otherwise you'd have to track whether
+ * a previous clear had happened at a different clear value and resolve it
+ * first.
+ */
+ if ((ctx->Scissor.EnableFlags & 1) && !noop_scissor(fb)) {
+ perf_debug("Failed to fast clear %dx%d depth because of scissors. "
+ "Possible 5%% performance win if avoided.\n",
+ mt->surf.logical_level0_px.width,
+ mt->surf.logical_level0_px.height);
+ return false;
}
- if (0)
- fprintf(stderr, "%s\n", __FUNCTION__);
+ switch (mt->format) {
+ case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
+ case MESA_FORMAT_Z24_UNORM_S8_UINT:
+ /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
+ *
+ * "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
+ * enabled (the legacy method of clearing must be performed):
+ *
+ * - If the depth buffer format is D32_FLOAT_S8X24_UINT or
+ * D24_UNORM_S8_UINT.
+ */
+ return false;
- /* Get SW clears out of the way: Anything without an intel_renderbuffer */
- for (i = 0; i < BUFFER_COUNT; i++) {
- if (!(mask & (1 << i)))
- continue;
+ case MESA_FORMAT_Z_UNORM16:
+ /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
+ *
+ * "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
+ * enabled (the legacy method of clearing must be performed):
+ *
+ * - DevSNB{W/A}]: When depth buffer format is D16_UNORM and the
+ * width of the map (LOD0) is not multiple of 16, fast clear
+ * optimization must be disabled.
+ */
+ if (devinfo->gen == 6 &&
+ (minify(mt->surf.phys_level0_sa.width,
+ depth_irb->mt_level - mt->first_level) % 16) != 0)
+ return false;
+ break;
- irb = intel_get_renderbuffer(fb, i);
- if (unlikely(!irb)) {
- swrast_mask |= (1 << i);
- mask &= ~(1 << i);
- }
- }
- if (unlikely(swrast_mask)) {
- debug_mask("swrast", swrast_mask);
- _swrast_Clear(ctx, swrast_mask);
+ default:
+ break;
}
- /* HW color buffers (front, back, aux, generic FBO, etc) */
- if (intel->gen < 6 && colorMask == ~0) {
- /* clear all R,G,B,A */
- blit_mask |= (mask & BUFFER_BITS_COLOR);
- }
- else {
- /* glColorMask in effect */
- tri_mask |= (mask & BUFFER_BITS_COLOR);
- }
+ /* Quantize the clear value to what can be stored in the actual depth
+ * buffer. This makes the following check more accurate because it now
+ * checks if the actual depth bits will match. It also prevents us from
+ * getting a too-accurate depth value during depth testing or when sampling
+ * with HiZ enabled.
+ */
+ float clear_value =
+ mt->format == MESA_FORMAT_Z_FLOAT32 ? ctx->Depth.Clear :
+ _mesa_lroundeven(ctx->Depth.Clear * fb->_DepthMax) / (float)(fb->_DepthMax);
- /* Make sure we have up to date buffers before we start looking at
- * the tiling bits to determine how to clear. */
- intel_prepare_render(intel);
-
- /* HW stencil */
- if (mask & BUFFER_BIT_STENCIL) {
- const struct intel_region *stencilRegion
- = intel_get_rb_region(fb, BUFFER_STENCIL);
- if (stencilRegion) {
- /* have hw stencil */
- if (stencilRegion->tiling == I915_TILING_Y ||
- (ctx->Stencil.WriteMask[0] & 0xff) != 0xff) {
- /* We have to use the 3D engine if we're clearing a partial mask
- * of the stencil buffer, or if we're on a 965 which has a tiled
- * depth/stencil buffer in a layout we can't blit to.
- */
- tri_mask |= BUFFER_BIT_STENCIL;
- }
- else if (intel->has_separate_stencil &&
- stencilRegion->tiling == I915_TILING_NONE) {
- /* The stencil buffer is actually W tiled, which the hardware
- * cannot blit to. */
- tri_mask |= BUFFER_BIT_STENCIL;
- }
- else {
- /* clearing all stencil bits, use blitting */
- blit_mask |= BUFFER_BIT_STENCIL;
+ const uint32_t num_layers = depth_att->Layered ? depth_irb->layer_count : 1;
+
+ /* If we're clearing to a new clear value, then we need to resolve any clear
+ * flags out of the HiZ buffer into the real depth buffer.
+ */
+ if (mt->fast_clear_color.f32[0] != clear_value) {
+ for (uint32_t level = mt->first_level; level <= mt->last_level; level++) {
+ if (!intel_miptree_level_has_hiz(mt, level))
+ continue;
+
+ const unsigned level_layers = brw_get_num_logical_layers(mt, level);
+
+ for (uint32_t layer = 0; layer < level_layers; layer++) {
+ if (level == depth_irb->mt_level &&
+ layer >= depth_irb->mt_layer &&
+ layer < depth_irb->mt_layer + num_layers) {
+ /* We're going to clear this layer anyway. Leave it alone. */
+ continue;
+ }
+
+ enum isl_aux_state aux_state =
+ intel_miptree_get_aux_state(mt, level, layer);
+
+ if (aux_state != ISL_AUX_STATE_CLEAR &&
+ aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) {
+ /* This slice doesn't have any fast-cleared bits. */
+ continue;
+ }
+
+ /* If we got here, then the level may have fast-clear bits that
+ * use the old clear value. We need to do a depth resolve to get
+ * rid of their use of the clear value before we can change it.
+ * Fortunately, few applications ever change their depth clear
+ * value so this shouldn't happen often.
+ */
+ intel_hiz_exec(brw, mt, level, layer, 1,
+ ISL_AUX_OP_FULL_RESOLVE);
+ intel_miptree_set_aux_state(brw, mt, level, layer, 1,
+ ISL_AUX_STATE_RESOLVED);
}
}
+
+ const union isl_color_value clear_color = { .f32 = {clear_value, } };
+ intel_miptree_set_clear_color(brw, mt, clear_color);
}
- /* HW depth */
- if (mask & BUFFER_BIT_DEPTH) {
- const struct intel_region *irb = intel_get_rb_region(fb, BUFFER_DEPTH);
+ for (unsigned a = 0; a < num_layers; a++) {
+ enum isl_aux_state aux_state =
+ intel_miptree_get_aux_state(mt, depth_irb->mt_level,
+ depth_irb->mt_layer + a);
- /* clear depth with whatever method is used for stencil (see above) */
- if (irb->tiling == I915_TILING_Y || tri_mask & BUFFER_BIT_STENCIL)
- tri_mask |= BUFFER_BIT_DEPTH;
- else
- blit_mask |= BUFFER_BIT_DEPTH;
+ if (aux_state != ISL_AUX_STATE_CLEAR) {
+ intel_hiz_exec(brw, mt, depth_irb->mt_level,
+ depth_irb->mt_layer + a, 1,
+ ISL_AUX_OP_FAST_CLEAR);
+ }
}
- /* If we're doing a tri pass for depth/stencil, include a likely color
- * buffer with it.
- */
- if (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)) {
- int color_bit = ffs(mask & BUFFER_BITS_COLOR);
- if (color_bit != 0) {
- tri_mask |= blit_mask & (1 << (color_bit - 1));
- blit_mask &= ~(1 << (color_bit - 1));
+ intel_miptree_set_aux_state(brw, mt, depth_irb->mt_level,
+ depth_irb->mt_layer, num_layers,
+ ISL_AUX_STATE_CLEAR);
+ return true;
+}
+
+/**
+ * Called by ctx->Driver.Clear.
+ */
+static void
+brw_clear(struct gl_context *ctx, GLbitfield mask)
+{
+ struct brw_context *brw = brw_context(ctx);
+ struct gl_framebuffer *fb = ctx->DrawBuffer;
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ bool partial_clear = ctx->Scissor.EnableFlags && !noop_scissor(fb);
+
+ if (!_mesa_check_conditional_render(ctx))
+ return;
+
+ if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
+ brw->front_buffer_dirty = true;
+ }
+
+ intel_prepare_render(brw);
+ brw_workaround_depthstencil_alignment(brw, partial_clear ? 0 : mask);
+
+ if (mask & BUFFER_BIT_DEPTH) {
+ if (brw_fast_clear_depth(ctx)) {
+ DBG("fast clear: depth\n");
+ mask &= ~BUFFER_BIT_DEPTH;
}
}
- /* Anything left, just use tris */
- tri_mask |= mask & ~blit_mask;
+ if (mask & BUFFER_BITS_COLOR) {
+ brw_blorp_clear_color(brw, fb, mask, partial_clear,
+ ctx->Color.sRGBEnabled);
+ debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
+ mask &= ~BUFFER_BITS_COLOR;
+ }
- if (blit_mask) {
- debug_mask("blit", blit_mask);
- tri_mask |= intelClearWithBlit(ctx, blit_mask);
+ if (devinfo->gen >= 6 && (mask & BUFFER_BITS_DEPTH_STENCIL)) {
+ brw_blorp_clear_depth_stencil(brw, fb, mask, partial_clear);
+ debug_mask("blorp depth/stencil", mask & BUFFER_BITS_DEPTH_STENCIL);
+ mask &= ~BUFFER_BITS_DEPTH_STENCIL;
}
+ GLbitfield tri_mask = mask & (BUFFER_BIT_STENCIL |
+ BUFFER_BIT_DEPTH);
+
if (tri_mask) {
debug_mask("tri", tri_mask);
- if (ctx->Extensions.ARB_fragment_shader)
- _mesa_meta_glsl_Clear(&intel->ctx, tri_mask);
- else
- _mesa_meta_Clear(&intel->ctx, tri_mask);
+ mask &= ~tri_mask;
+ _mesa_meta_glsl_Clear(&brw->ctx, tri_mask);
+ }
+
+ /* Any strange buffers get passed off to swrast. The only thing that
+ * should be left at this point is the accumulation buffer.
+ */
+ assert((mask & ~BUFFER_BIT_ACCUM) == 0);
+ if (mask) {
+ debug_mask("swrast", mask);
+ _swrast_Clear(ctx, mask);
}
}
void
intelInitClearFuncs(struct dd_function_table *functions)
{
- functions->Clear = intelClear;
+ functions->Clear = brw_clear;
}
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