#include "drivers/common/meta.h"
#include "intel_batchbuffer.h"
-#include "intel_blit.h"
#include "intel_fbo.h"
#include "intel_mipmap_tree.h"
intel_get_renderbuffer(fb, BUFFER_DEPTH);
struct intel_mipmap_tree *mt = depth_irb->mt;
struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH];
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
- if (brw->gen < 6)
+ if (INTEL_DEBUG & DEBUG_NO_FAST_CLEAR)
+ return false;
+
+ if (devinfo->gen < 6)
return false;
if (!intel_renderbuffer_has_hiz(depth_irb))
if ((ctx->Scissor.EnableFlags & 1) && !noop_scissor(fb)) {
perf_debug("Failed to fast clear %dx%d depth because of scissors. "
"Possible 5%% performance win if avoided.\n",
- mt->logical_width0, mt->logical_height0);
+ mt->surf.logical_level0_px.width,
+ mt->surf.logical_level0_px.height);
return false;
}
* width of the map (LOD0) is not multiple of 16, fast clear
* optimization must be disabled.
*/
- if (brw->gen == 6 &&
- (minify(mt->physical_width0,
+ if (devinfo->gen == 6 &&
+ (minify(mt->surf.phys_level0_sa.width,
depth_irb->mt_level - mt->first_level) % 16) != 0)
return false;
break;
break;
}
+ /* Quantize the clear value to what can be stored in the actual depth
+ * buffer. This makes the following check more accurate because it now
+ * checks if the actual depth bits will match. It also prevents us from
+ * getting a too-accurate depth value during depth testing or when sampling
+ * with HiZ enabled.
+ */
+ float clear_value =
+ mt->format == MESA_FORMAT_Z_FLOAT32 ? ctx->Depth.Clear :
+ _mesa_lroundeven(ctx->Depth.Clear * fb->_DepthMax) / (float)(fb->_DepthMax);
+
+ const uint32_t num_layers = depth_att->Layered ? depth_irb->layer_count : 1;
+
/* If we're clearing to a new clear value, then we need to resolve any clear
* flags out of the HiZ buffer into the real depth buffer.
*/
- if (mt->fast_clear_color.f32[0] != ctx->Depth.Clear) {
- intel_miptree_all_slices_resolve_depth(brw, mt);
- mt->fast_clear_color.f32[0] = ctx->Depth.Clear;
- }
-
- if (brw->gen == 6) {
- /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
- *
- * "If other rendering operations have preceded this clear, a
- * PIPE_CONTROL with write cache flush enabled and Z-inhibit disabled
- * must be issued before the rectangle primitive used for the depth
- * buffer clear operation.
- */
- brw_emit_pipe_control_flush(brw,
- PIPE_CONTROL_RENDER_TARGET_FLUSH |
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- PIPE_CONTROL_CS_STALL);
- } else if (brw->gen >= 7) {
- /*
- * From the Ivybridge PRM, volume 2, "Depth Buffer Clear":
- *
- * If other rendering operations have preceded this clear, a
- * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
- * enabled must be issued before the rectangle primitive used for the
- * depth buffer clear operation.
- *
- * Same applies for Gen8 and Gen9.
- *
- * In addition, from the Ivybridge PRM, volume 2, 1.10.4.1 PIPE_CONTROL,
- * Depth Cache Flush Enable:
- *
- * This bit must not be set when Depth Stall Enable bit is set in
- * this packet.
- *
- * This is confirmed to hold for real, HSW gets immediate gpu hangs.
- *
- * Therefore issue two pipe control flushes, one for cache flush and
- * another for depth stall.
- */
- brw_emit_pipe_control_flush(brw,
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- PIPE_CONTROL_CS_STALL);
+ if (mt->fast_clear_color.f32[0] != clear_value) {
+ for (uint32_t level = mt->first_level; level <= mt->last_level; level++) {
+ if (!intel_miptree_level_has_hiz(mt, level))
+ continue;
+
+ const unsigned level_layers = brw_get_num_logical_layers(mt, level);
+
+ for (uint32_t layer = 0; layer < level_layers; layer++) {
+ if (level == depth_irb->mt_level &&
+ layer >= depth_irb->mt_layer &&
+ layer < depth_irb->mt_layer + num_layers) {
+ /* We're going to clear this layer anyway. Leave it alone. */
+ continue;
+ }
+
+ enum isl_aux_state aux_state =
+ intel_miptree_get_aux_state(mt, level, layer);
+
+ if (aux_state != ISL_AUX_STATE_CLEAR &&
+ aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) {
+ /* This slice doesn't have any fast-cleared bits. */
+ continue;
+ }
+
+ /* If we got here, then the level may have fast-clear bits that
+ * use the old clear value. We need to do a depth resolve to get
+ * rid of their use of the clear value before we can change it.
+ * Fortunately, few applications ever change their depth clear
+ * value so this shouldn't happen often.
+ */
+ intel_hiz_exec(brw, mt, level, layer, 1,
+ ISL_AUX_OP_FULL_RESOLVE);
+ intel_miptree_set_aux_state(brw, mt, level, layer, 1,
+ ISL_AUX_STATE_RESOLVED);
+ }
+ }
- brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
+ const union isl_color_value clear_color = { .f32 = {clear_value, } };
+ intel_miptree_set_clear_color(brw, mt, clear_color);
}
- if (fb->MaxNumLayers > 0) {
- intel_hiz_exec(brw, mt, depth_irb->mt_level,
- depth_irb->mt_layer, depth_irb->layer_count,
- BLORP_HIZ_OP_DEPTH_CLEAR);
- } else {
- intel_hiz_exec(brw, mt, depth_irb->mt_level, depth_irb->mt_layer, 1,
- BLORP_HIZ_OP_DEPTH_CLEAR);
- }
+ for (unsigned a = 0; a < num_layers; a++) {
+ enum isl_aux_state aux_state =
+ intel_miptree_get_aux_state(mt, depth_irb->mt_level,
+ depth_irb->mt_layer + a);
- if (brw->gen == 6) {
- /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
- *
- * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be followed
- * by a PIPE_CONTROL command with DEPTH_STALL bit set and Then
- * followed by Depth FLUSH'
- */
- brw_emit_pipe_control_flush(brw,
- PIPE_CONTROL_DEPTH_STALL);
-
- brw_emit_pipe_control_flush(brw,
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- PIPE_CONTROL_CS_STALL);
+ if (aux_state != ISL_AUX_STATE_CLEAR) {
+ intel_hiz_exec(brw, mt, depth_irb->mt_level,
+ depth_irb->mt_layer + a, 1,
+ ISL_AUX_OP_FAST_CLEAR);
+ }
}
- /* Now, the HiZ buffer contains data that needs to be resolved to the depth
- * buffer.
- */
- intel_renderbuffer_att_set_needs_depth_resolve(depth_att);
-
+ intel_miptree_set_aux_state(brw, mt, depth_irb->mt_level,
+ depth_irb->mt_layer, num_layers,
+ ISL_AUX_STATE_CLEAR);
return true;
}
{
struct brw_context *brw = brw_context(ctx);
struct gl_framebuffer *fb = ctx->DrawBuffer;
+ const struct gen_device_info *devinfo = &brw->screen->devinfo;
bool partial_clear = ctx->Scissor.EnableFlags && !noop_scissor(fb);
if (!_mesa_check_conditional_render(ctx))
}
}
- if (mask & BUFFER_BIT_STENCIL) {
- struct intel_renderbuffer *stencil_irb =
- intel_get_renderbuffer(fb, BUFFER_STENCIL);
- struct intel_mipmap_tree *mt = stencil_irb->mt;
- if (mt && mt->stencil_mt)
- mt->stencil_mt->r8stencil_needs_update = true;
+ if (mask & BUFFER_BITS_COLOR) {
+ brw_blorp_clear_color(brw, fb, mask, partial_clear,
+ ctx->Color.sRGBEnabled);
+ debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
+ mask &= ~BUFFER_BITS_COLOR;
}
- if (mask & BUFFER_BITS_COLOR) {
- const bool encode_srgb = ctx->Color.sRGBEnabled;
- if (brw_blorp_clear_color(brw, fb, mask, partial_clear, encode_srgb)) {
- debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
- mask &= ~BUFFER_BITS_COLOR;
- }
+ if (devinfo->gen >= 6 && (mask & BUFFER_BITS_DEPTH_STENCIL)) {
+ brw_blorp_clear_depth_stencil(brw, fb, mask, partial_clear);
+ debug_mask("blorp depth/stencil", mask & BUFFER_BITS_DEPTH_STENCIL);
+ mask &= ~BUFFER_BITS_DEPTH_STENCIL;
}
- GLbitfield tri_mask = mask & (BUFFER_BITS_COLOR |
- BUFFER_BIT_STENCIL |
- BUFFER_BIT_DEPTH);
+ GLbitfield tri_mask = mask & (BUFFER_BIT_STENCIL |
+ BUFFER_BIT_DEPTH);
if (tri_mask) {
debug_mask("tri", tri_mask);
mask &= ~tri_mask;
-
- if (ctx->API == API_OPENGLES) {
- _mesa_meta_Clear(&brw->ctx, tri_mask);
- } else {
- _mesa_meta_glsl_Clear(&brw->ctx, tri_mask);
- }
+ _mesa_meta_glsl_Clear(&brw->ctx, tri_mask);
}
- /* Any strange buffers get passed off to swrast */
+ /* Any strange buffers get passed off to swrast. The only thing that
+ * should be left at this point is the accumulation buffer.
+ */
+ assert((mask & ~BUFFER_BIT_ACCUM) == 0);
if (mask) {
debug_mask("swrast", mask);
_swrast_Clear(ctx, mask);
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