i965/vec4: Make with_writemask() non-static.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_clear.c

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index 216ab9e93a999affaf98360f2140fa1d4907a69f..a727e6ec41cd4410fe2d6057337526da1c150e41 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -109,6 +109,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
    struct intel_renderbuffer *depth_irb =
       intel_get_renderbuffer(fb, BUFFER_DEPTH);
    struct intel_mipmap_tree *mt = depth_irb->mt;
+   struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH];
 
    if (brw->gen < 6)
       return false;
@@ -196,7 +197,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
    /* Now, the HiZ buffer contains data that needs to be resolved to the depth
     * buffer.
     */
-   intel_renderbuffer_set_needs_depth_resolve(depth_irb);
+   intel_renderbuffer_att_set_needs_depth_resolve(depth_att);
 
    return true;
 }
@@ -208,7 +209,6 @@ static void
 brw_clear(struct gl_context *ctx, GLbitfield mask)
 {
    struct brw_context *brw = brw_context(ctx);
-   struct intel_context *intel = &brw->intel;
    struct gl_framebuffer *fb = ctx->DrawBuffer;
    bool partial_clear = ctx->Scissor.Enabled && !noop_scissor(ctx, fb);
 
@@ -248,9 +248,9 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
       mask &= ~tri_mask;
 
       if (ctx->API == API_OPENGLES) {
-         _mesa_meta_Clear(&intel->ctx, tri_mask);
+         _mesa_meta_Clear(&brw->ctx, tri_mask);
       } else {
-         _mesa_meta_glsl_Clear(&intel->ctx, tri_mask);
+         _mesa_meta_glsl_Clear(&brw->ctx, tri_mask);
       }
    }