i965/vec4: Make with_writemask() non-static.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_clear.c

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index f68969157e1f25edc64df3e1b282d889c1fe8ed6..a727e6ec41cd4410fe2d6057337526da1c150e41 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -105,13 +105,13 @@ static bool
 brw_fast_clear_depth(struct gl_context *ctx)
 {
    struct brw_context *brw = brw_context(ctx);
-   struct intel_context *intel = intel_context(ctx);
    struct gl_framebuffer *fb = ctx->DrawBuffer;
    struct intel_renderbuffer *depth_irb =
       intel_get_renderbuffer(fb, BUFFER_DEPTH);
    struct intel_mipmap_tree *mt = depth_irb->mt;
+   struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH];
 
-   if (intel->gen < 6)
+   if (brw->gen < 6)
       return false;
 
    if (!intel_renderbuffer_has_hiz(depth_irb))
@@ -155,7 +155,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
        *        width of the map (LOD0) is not multiple of 16, fast clear
        *        optimization must be disabled.
        */
-      if (intel->gen == 6 && (mt->level[depth_irb->mt_level].width % 16) != 0)
+      if (brw->gen == 6 && (mt->level[depth_irb->mt_level].width % 16) != 0)
         return false;
       /* FALLTHROUGH */
 
@@ -184,7 +184,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
    intel_hiz_exec(brw, mt, depth_irb->mt_level, depth_irb->mt_layer,
                  GEN6_HIZ_OP_DEPTH_CLEAR);
 
-   if (intel->gen == 6) {
+   if (brw->gen == 6) {
       /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
        *
        *     "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be followed
@@ -197,7 +197,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
    /* Now, the HiZ buffer contains data that needs to be resolved to the depth
     * buffer.
     */
-   intel_renderbuffer_set_needs_depth_resolve(depth_irb);
+   intel_renderbuffer_att_set_needs_depth_resolve(depth_att);
 
    return true;
 }
@@ -209,7 +209,6 @@ static void
 brw_clear(struct gl_context *ctx, GLbitfield mask)
 {
    struct brw_context *brw = brw_context(ctx);
-   struct intel_context *intel = &brw->intel;
    struct gl_framebuffer *fb = ctx->DrawBuffer;
    bool partial_clear = ctx->Scissor.Enabled && !noop_scissor(ctx, fb);
 
@@ -217,7 +216,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
       return;
 
    if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
-      intel->front_buffer_dirty = true;
+      brw->front_buffer_dirty = true;
    }
 
    intel_prepare_render(brw);
@@ -231,7 +230,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
    }
 
    /* BLORP is currently only supported on Gen6+. */
-   if (intel->gen >= 6) {
+   if (brw->gen >= 6) {
       if (mask & BUFFER_BITS_COLOR) {
          if (brw_blorp_clear_color(brw, fb, partial_clear)) {
             debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
@@ -249,9 +248,9 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
       mask &= ~tri_mask;
 
       if (ctx->API == API_OPENGLES) {
-         _mesa_meta_Clear(&intel->ctx, tri_mask);
+         _mesa_meta_Clear(&brw->ctx, tri_mask);
       } else {
-         _mesa_meta_glsl_Clear(&intel->ctx, tri_mask);
+         _mesa_meta_glsl_Clear(&brw->ctx, tri_mask);
       }
    }