i965/fs: Lower 32x32 bit multiplication on BXT.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_clear.c

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index a1c1d0131b208889bb0795a5346139dd8f9389ba..f981388ef1a2d76eee1324c22ac78e822ec89ec3 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -121,8 +121,9 @@ brw_fast_clear_depth(struct gl_context *ctx)
     * first.
     */
    if ((ctx->Scissor.EnableFlags & 1) && !noop_scissor(ctx, fb)) {
-      perf_debug("Failed to fast clear depth due to scissor being enabled.  "
-                 "Possible 5%% performance win if avoided.\n");
+      perf_debug("Failed to fast clear %dx%d depth because of scissors.  "
+                 "Possible 5%% performance win if avoided.\n",
+                 mt->logical_width0, mt->logical_height0);
       return false;
    }
 
@@ -183,7 +184,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
     *      must be issued before the rectangle primitive used for the depth
     *      buffer clear operation.
     */
-   intel_batchbuffer_emit_mi_flush(brw);
+   brw_emit_mi_flush(brw);
 
    if (fb->MaxNumLayers > 0) {
       for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) {
@@ -203,7 +204,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
        *      by a PIPE_CONTROL command with DEPTH_STALL bit set and Then
        *      followed by Depth FLUSH'
       */
-      intel_batchbuffer_emit_mi_flush(brw);
+      brw_emit_mi_flush(brw);
    }
 
    /* Now, the HiZ buffer contains data that needs to be resolved to the depth
@@ -241,13 +242,11 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
       }
    }
 
-   /* BLORP is currently only supported on Gen6+. */
-   if (brw->gen >= 6 && brw->gen < 8) {
-      if (mask & BUFFER_BITS_COLOR) {
-         if (brw_blorp_clear_color(brw, fb, mask, partial_clear)) {
-            debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
-            mask &= ~BUFFER_BITS_COLOR;
-         }
+   /* Clear color buffers with fast clear or at least rep16 writes. */
+   if (brw->gen >= 6 && brw->gen < 9 && (mask & BUFFER_BITS_COLOR)) {
+      if (brw_meta_fast_clear(brw, fb, mask, partial_clear)) {
+         debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
+         mask &= ~BUFFER_BITS_COLOR;
       }
    }