#include "brw_state.h"
#include "brw_clip.h"
-
#define FRONT_UNFILLED_BIT 0x1
#define BACK_UNFILLED_BIT 0x2
static void compile_clip_prog( struct brw_context *brw,
struct brw_clip_prog_key *key )
{
+ struct intel_context *intel = &brw->intel;
struct brw_clip_compile c;
const GLuint *program;
GLuint program_size;
GLuint delta;
GLuint i;
+ GLuint header_regs;
memset(&c, 0, sizeof(c));
c.func.single_program_flow = 1;
c.key = *key;
- c.need_ff_sync = BRW_IS_IGDNG(brw);
/* Need to locate the two positions present in vertex + header.
* These are currently hardcoded:
*/
c.header_position_offset = ATTR_SIZE;
- if (BRW_IS_IGDNG(brw))
- delta = 3 * REG_SIZE;
+ if (intel->gen == 5)
+ header_regs = 3;
else
- delta = REG_SIZE;
+ header_regs = 1;
+
+ delta = header_regs * REG_SIZE;
- for (i = 0; i < VERT_RESULT_MAX; i++)
- if (c.key.attrs & (1<<i)) {
+ for (i = 0; i < VERT_RESULT_MAX; i++) {
+ if (c.key.attrs & BITFIELD64_BIT(i)) {
c.offset[i] = delta;
delta += ATTR_SIZE;
+
+ c.idx_to_attr[c.nr_attrs] = i;
+ c.nr_attrs++;
}
+ }
- c.nr_attrs = brw_count_bits(c.key.attrs);
-
- if (BRW_IS_IGDNG(brw))
- c.nr_regs = (c.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */
- else
- c.nr_regs = (c.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */
+ /* The vertex attributes start at a URB row-aligned offset after
+ * the 8-20 dword vertex header, and continue for a URB row-aligned
+ * length. nr_regs determines the urb_read_length from the start
+ * of the header to the end of the vertex data.
+ */
+ c.nr_regs = header_regs + (c.nr_attrs + 1) / 2;
c.nr_bytes = c.nr_regs * REG_SIZE;
*/
program = brw_get_program(&c.func, &program_size);
+ if (INTEL_DEBUG & DEBUG_CLIP) {
+ printf("clip:\n");
+ for (i = 0; i < program_size / sizeof(struct brw_instruction); i++)
+ brw_disasm(stdout, &((struct brw_instruction *)program)[i],
+ intel->gen);
+ printf("\n");
+ }
+
/* Upload
*/
- dri_bo_unreference(brw->clip.prog_bo);
- brw->clip.prog_bo = brw_upload_cache( &brw->cache,
- BRW_CLIP_PROG,
- &c.key, sizeof(c.key),
- NULL, 0,
- program, program_size,
- &c.prog_data,
- &brw->clip.prog_data );
+ drm_intel_bo_unreference(brw->clip.prog_bo);
+ brw->clip.prog_bo = brw_upload_cache_with_auxdata(&brw->cache,
+ BRW_CLIP_PROG,
+ &c.key, sizeof(c.key),
+ NULL, 0,
+ program, program_size,
+ &c.prog_data,
+ sizeof(c.prog_data),
+ &brw->clip.prog_data);
}
/* Calculate interpolants for triangle and line rasterization.
*/
static void upload_clip_prog(struct brw_context *brw)
{
- GLcontext *ctx = &brw->intel.ctx;
+ struct intel_context *intel = &brw->intel;
+ struct gl_context *ctx = &intel->ctx;
struct brw_clip_prog_key key;
memset(&key, 0, sizeof(key));
key.attrs = brw->vs.prog_data->outputs_written;
/* _NEW_LIGHT */
key.do_flat_shading = (ctx->Light.ShadeModel == GL_FLAT);
+ key.pv_first = (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION);
/* _NEW_TRANSFORM */
key.nr_userclip = brw_count_bits(ctx->Transform.ClipPlanesEnabled);
- if (BRW_IS_IGDNG(brw))
+ if (intel->gen == 5)
key.clip_mode = BRW_CLIPMODE_KERNEL_CLIP;
else
key.clip_mode = BRW_CLIPMODE_NORMAL;
}
}
- dri_bo_unreference(brw->clip.prog_bo);
+ drm_intel_bo_unreference(brw->clip.prog_bo);
brw->clip.prog_bo = brw_search_cache(&brw->cache, BRW_CLIP_PROG,
&key, sizeof(key),
NULL, 0,