intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_clip_line.c

diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c
index 8466b1c74c863a2aca8369781d75bad329e63e63..5238598132bea24cc243c976bdeaf69c16a0fe57 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clip_line.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_line.c
@@ -282,10 +282,10 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
       brw_clip_interp_vertex(c, newvtx0, vtx0, vtx1, c->reg.t0, false);
       brw_clip_interp_vertex(c, newvtx1, vtx1, vtx0, c->reg.t1, false);
 
-      brw_clip_emit_vue(c, newvtx0, 1, 0,
+      brw_clip_emit_vue(c, newvtx0, BRW_URB_WRITE_ALLOCATE_COMPLETE,
                         (_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
                         | URB_WRITE_PRIM_START);
-      brw_clip_emit_vue(c, newvtx1, 0, 1,
+      brw_clip_emit_vue(c, newvtx1, BRW_URB_WRITE_EOT_COMPLETE,
                         (_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
                         | URB_WRITE_PRIM_END);
    }