i965/gs: Add a case to brwNewProgram() for geometry shaders.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_clip_state.c

diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index 7f6674322fe425473e5f3fa1e10b8386e010dba2..634719bd031b7026f39cafa3fc57287bbb99c604 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -36,8 +36,7 @@
 static void
 upload_clip_vp(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &intel->ctx;
+   struct gl_context *ctx = &brw->ctx;
    struct brw_clipper_viewport *vp;
 
    vp = brw_state_batch(brw, AUB_TRACE_CLIP_VP_STATE,
@@ -56,8 +55,7 @@ upload_clip_vp(struct brw_context *brw)
 static void
 brw_upload_clip_unit(struct brw_context *brw)
 {
-   struct intel_context *intel = &brw->intel;
-   struct gl_context *ctx = &intel->ctx;
+   struct gl_context *ctx = &brw->ctx;
    struct brw_clip_unit_state *clip;
 
    /* _NEW_BUFFERS */
@@ -105,7 +103,7 @@ brw_upload_clip_unit(struct brw_context *brw)
       /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
        * only 2 threads can output VUEs at a time.
        */
-      if (intel->gen == 5)
+      if (brw->gen == 5)
          clip->thread4.max_threads = 16 - 1;
       else
          clip->thread4.max_threads = 2 - 1;
@@ -117,7 +115,13 @@ brw_upload_clip_unit(struct brw_context *brw)
    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
       clip->thread4.stats_enable = 1;
 
-   clip->clip5.userclip_enable_flags = 0x7f;
+   /* _NEW_TRANSFORM */
+   if (brw->gen == 5 || brw->is_g4x)
+      clip->clip5.userclip_enable_flags = ctx->Transform.ClipPlanesEnabled;
+   else
+      /* Up to 6 actual clip flags, plus the 7th for negative RHW workaround. */
+      clip->clip5.userclip_enable_flags = (ctx->Transform.ClipPlanesEnabled & 0x3f) | 0x40;
+
    clip->clip5.userclip_must_clip = 1;
 
    /* enable guardband clipping if we can */
@@ -128,13 +132,13 @@ brw_upload_clip_unit(struct brw_context *brw)
    {
       clip->clip5.guard_band_enable = 1;
       clip->clip6.clipper_viewport_state_ptr =
-         (intel->batch.bo->offset + brw->clip.vp_offset) >> 5;
+         (brw->batch.bo->offset + brw->clip.vp_offset) >> 5;
 
       /* emit clip viewport relocation */
-      drm_intel_bo_emit_reloc(brw->intel.batch.bo,
+      drm_intel_bo_emit_reloc(brw->batch.bo,
                               (brw->clip.state_offset +
                                offsetof(struct brw_clip_unit_state, clip6)),
-                              intel->batch.bo, brw->clip.vp_offset,
+                              brw->batch.bo, brw->clip.vp_offset,
                               I915_GEM_DOMAIN_INSTRUCTION, 0);
    }
 
@@ -146,7 +150,7 @@ brw_upload_clip_unit(struct brw_context *brw)
    clip->clip5.api_mode = BRW_CLIP_API_OGL;
    clip->clip5.clip_mode = brw->clip.prog_data->clip_mode;
 
-   if (intel->is_g4x)
+   if (brw->is_g4x)
       clip->clip5.negative_w_clip_test = 1;
 
    clip->viewport_xmin = -1;