Merge remote branch 'origin/master' into lp-setup-llvm

[mesa.git] / src / mesa / drivers / dri / i965 / brw_clip_tri.c

diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c
index 8d5ca41896a049a3f747f34fc925f6c6875fe133..cb58d1da9fef3709c1965e46397a2c5869828387 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clip_tri.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c
@@ -32,7 +32,7 @@
 #include "main/glheader.h"
 #include "main/macros.h"
 #include "main/enums.h"
-#include "shader/program.h"
+#include "program/program.h"
 
 #include "intel_batchbuffer.h"
 
@@ -50,6 +50,7 @@ static void release_tmps( struct brw_clip_compile *c )
 void brw_clip_tri_alloc_regs( struct brw_clip_compile *c, 
                              GLuint nr_verts )
 {
+   struct intel_context *intel = &c->func.brw->intel;
    GLuint i = 0,j;
 
    /* Register usage is static, precompute here:
@@ -75,10 +76,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
 
    if (c->nr_attrs & 1) {
       for (j = 0; j < 3; j++) {
-        GLuint delta = c->nr_attrs*16 + 32;
-
-         if (BRW_IS_IGDNG(c->func.brw))
-             delta = c->nr_attrs * 16 + 32 * 3;
+        GLuint delta = c->offset[c->idx_to_attr[c->nr_attrs - 1]] + ATTR_SIZE;
 
         brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0));
       }
@@ -118,7 +116,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
       i++;
    }
 
-   if (c->need_ff_sync) {
+   if (intel->needs_ff_sync) {
       c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD);
       i++;
    }
@@ -176,7 +174,7 @@ void brw_clip_tri_init_vertices( struct brw_clip_compile *c )
 void brw_clip_tri_flat_shade( struct brw_clip_compile *c )
 {
    struct brw_compile *p = &c->func;
-   struct brw_instruction *is_poly;
+   struct brw_instruction *is_poly, *is_trifan;
    struct brw_reg tmp0 = c->reg.loopcount; /* handy temporary */
 
    brw_AND(p, tmp0, get_element_ud(c->reg.R0, 2), brw_imm_ud(PRIM_MASK)); 
@@ -194,8 +192,22 @@ void brw_clip_tri_flat_shade( struct brw_clip_compile *c )
    is_poly = brw_ELSE(p, is_poly);
    {
       if (c->key.pv_first) {
-         brw_clip_copy_colors(c, 1, 0);
-         brw_clip_copy_colors(c, 2, 0);
+        brw_CMP(p,
+                vec1(brw_null_reg()),
+                BRW_CONDITIONAL_EQ,
+                tmp0,
+                brw_imm_ud(_3DPRIM_TRIFAN));
+        is_trifan = brw_IF(p, BRW_EXECUTE_1);
+        {
+           brw_clip_copy_colors(c, 0, 1);
+           brw_clip_copy_colors(c, 2, 1);
+        }
+        is_trifan = brw_ELSE(p, is_trifan);
+        {
+           brw_clip_copy_colors(c, 1, 0);
+           brw_clip_copy_colors(c, 2, 0);
+        }
+        brw_ENDIF(p, is_trifan);
       }
       else {
          brw_clip_copy_colors(c, 0, 2);
@@ -570,6 +582,7 @@ void brw_emit_tri_clip( struct brw_clip_compile *c )
 {
    struct brw_instruction *neg_rhw;
    struct brw_compile *p = &c->func;
+   struct brw_context *brw = p->brw;
    brw_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6);
    brw_clip_tri_init_vertices(c);
    brw_clip_init_clipmask(c);
@@ -577,7 +590,7 @@ void brw_emit_tri_clip( struct brw_clip_compile *c )
 
    /* if -ve rhw workaround bit is set, 
       do cliptest */
-   if (BRW_IS_965(p->brw)) {
+   if (brw->has_negative_rhw_bug) {
       brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
       brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), 
               brw_imm_ud(1<<20));