/*
Copyright (C) Intel Corp. 2006. All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
+ Intel funded Tungsten Graphics to
develop this 3D driver.
Permission is hereby granted, free of charge, to any person obtaining
**********************************************************************/
/*
* Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
+ * Keith Whitwell <keithw@vmware.com>
*/
void brw_clip_init_planes( struct brw_clip_compile *c )
{
- struct brw_compile *p = &c->func;
+ struct brw_codegen *p = &c->func;
if (!c->key.nr_userclip) {
brw_MOV(p, get_element_ud(c->reg.fixed_planes, 0), make_plane_ud( 0, 0, 0xff, 1));
*/
void brw_clip_project_position(struct brw_clip_compile *c, struct brw_reg pos )
{
- struct brw_compile *p = &c->func;
+ struct brw_codegen *p = &c->func;
/* calc rhw
*/
/* value.xyz *= value.rhw
*/
- brw_set_access_mode(p, BRW_ALIGN_16);
+ brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_MUL(p, brw_writemask(pos, WRITEMASK_XYZ), pos, brw_swizzle1(pos, W));
- brw_set_access_mode(p, BRW_ALIGN_1);
+ brw_set_default_access_mode(p, BRW_ALIGN_1);
}
static void brw_clip_project_vertex( struct brw_clip_compile *c,
struct brw_indirect vert_addr )
{
- struct brw_compile *p = &c->func;
+ struct brw_codegen *p = &c->func;
struct brw_reg tmp = get_tmp(c);
GLuint hpos_offset = brw_varying_to_offset(&c->vue_map, VARYING_SLOT_POS);
GLuint ndc_offset = brw_varying_to_offset(&c->vue_map,
struct brw_reg t0,
bool force_edgeflag)
{
- struct brw_compile *p = &c->func;
+ struct brw_codegen *p = &c->func;
struct brw_reg t_nopersp, v0_ndc_copy;
GLuint slot;
/* t_nopersp = vec4(v1.xy, dest.xy) */
brw_MOV(p, t_nopersp, deref_4f(v1_ptr, delta));
brw_MOV(p, tmp, deref_4f(dest_ptr, delta));
- brw_set_access_mode(p, BRW_ALIGN_16);
+ brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_MOV(p,
brw_writemask(t_nopersp, WRITEMASK_ZW),
brw_swizzle(tmp, 0, 1, 0, 1));
brw_writemask(t_nopersp, WRITEMASK_XY),
brw_abs(brw_swizzle(t_nopersp, 0, 2, 0, 0)),
brw_abs(brw_swizzle(t_nopersp, 1, 3, 0, 0)));
- brw_set_access_mode(p, BRW_ALIGN_1);
+ brw_set_default_access_mode(p, BRW_ALIGN_1);
/* If the points are in the same place, just substitute a
* value to avoid divide-by-zero
vec1(t_nopersp),
brw_imm_f(0));
brw_IF(p, BRW_EXECUTE_1);
- brw_MOV(p, t_nopersp, brw_imm_vf4(VF_ONE, VF_ZERO, VF_ZERO, VF_ZERO));
+ brw_MOV(p, t_nopersp, brw_imm_vf4(1, 0, 0, 0));
brw_ENDIF(p);
/* Now compute t_nopersp = t_nopersp.y/t_nopersp.x and broadcast it. */
brw_math_invert(p, get_element(t_nopersp, 0), get_element(t_nopersp, 0));
brw_MUL(p, vec1(t_nopersp), vec1(t_nopersp),
vec1(suboffset(t_nopersp, 1)));
- brw_set_access_mode(p, BRW_ALIGN_16);
+ brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_MOV(p, t_nopersp, brw_swizzle(t_nopersp, 0, 0, 0, 0));
- brw_set_access_mode(p, BRW_ALIGN_1);
+ brw_set_default_access_mode(p, BRW_ALIGN_1);
release_tmp(c, tmp);
release_tmp(c, v0_ndc_copy);
enum brw_urb_write_flags flags,
GLuint header)
{
- struct brw_compile *p = &c->func;
+ struct brw_codegen *p = &c->func;
bool allocate = flags & BRW_URB_WRITE_ALLOCATE;
brw_clip_ff_sync(c);
brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header));
- /* Send each vertex as a seperate write to the urb. This
+ /* Send each vertex as a separate write to the urb. This
* is different to the concept in brw_sf_emit.c, where
* subsequent writes are used to build up a single urb
- * entry. Each of these writes instantiates a seperate
+ * entry. Each of these writes instantiates a separate
* urb entry - (I think... what about 'allocate'?)
*/
brw_urb_WRITE(p,
void brw_clip_kill_thread(struct brw_clip_compile *c)
{
- struct brw_compile *p = &c->func;
+ struct brw_codegen *p = &c->func;
brw_clip_ff_sync(c);
/* Send an empty message to kill the thread and release any
void brw_clip_copy_flatshaded_attributes( struct brw_clip_compile *c,
GLuint to, GLuint from )
{
- struct brw_compile *p = &c->func;
+ struct brw_codegen *p = &c->func;
for (int i = 0; i < c->vue_map.num_slots; i++) {
if (c->key.interpolation_mode.mode[i] == INTERP_QUALIFIER_FLAT) {
void brw_clip_init_clipmask( struct brw_clip_compile *c )
{
- struct brw_compile *p = &c->func;
+ struct brw_codegen *p = &c->func;
struct brw_reg incoming = get_element_ud(c->reg.R0, 2);
- struct brw_context *brw = p->brw;
/* Shift so that lowest outcode bit is rightmost:
*/
/* Rearrange userclip outcodes so that they come directly after
* the fixed plane bits.
*/
- if (brw->gen == 5 || brw->is_g4x)
+ if (p->devinfo->gen == 5 || p->devinfo->is_g4x)
brw_AND(p, tmp, incoming, brw_imm_ud(0xff<<14));
else
brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14));
void brw_clip_ff_sync(struct brw_clip_compile *c)
{
- struct brw_compile *p = &c->func;
- struct brw_context *brw = p->brw;
+ struct brw_codegen *p = &c->func;
- if (brw->gen == 5) {
- brw_set_conditionalmod(p, BRW_CONDITIONAL_Z);
+ if (p->devinfo->gen == 5) {
brw_AND(p, brw_null_reg(), c->reg.ff_sync, brw_imm_ud(0x1));
+ brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_Z);
brw_IF(p, BRW_EXECUTE_1);
{
brw_OR(p, c->reg.ff_sync, c->reg.ff_sync, brw_imm_ud(0x1));
0 /* eot */);
}
brw_ENDIF(p);
- brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+ brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
}
}
void brw_clip_init_ff_sync(struct brw_clip_compile *c)
{
- struct brw_context *brw = c->func.brw;
-
- if (brw->gen == 5) {
- struct brw_compile *p = &c->func;
+ struct brw_codegen *p = &c->func;
+ if (p->devinfo->gen == 5) {
brw_MOV(p, c->reg.ff_sync, brw_imm_ud(0));
}
}
projects / mesa.git / blobdiff