i965/gs: Add a case to brwNewProgram() for geometry shaders.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_clip_util.c

diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c b/src/mesa/drivers/dri/i965/brw_clip_util.c
index 8500b8b6663e11c8a402b5910fe4d30af1418de9..62172ecf6b876ce05c95cf809d05f0af3682459b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clip_util.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_util.c
@@ -256,13 +256,9 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
            brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(1));
         else
            brw_MOV(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta));
-      } else if (varying == VARYING_SLOT_PSIZ ||
-                 varying == VARYING_SLOT_CLIP_DIST0 ||
-                 varying == VARYING_SLOT_CLIP_DIST1) {
-        /* PSIZ doesn't need interpolation because it isn't used by the
-          * fragment shader.  CLIP_DIST0 and CLIP_DIST1 don't need
-          * intepolation because on pre-GEN6, these are just placeholder VUE
-          * slots that don't perform any action.
+      } else if (varying == VARYING_SLOT_PSIZ) {
+         /* PSIZ doesn't need interpolation because it isn't used by the
+          * fragment shader.
           */
       } else if (varying < VARYING_SLOT_MAX) {
         /* This is a true vertex result (and not a special value for the VUE
@@ -424,6 +420,7 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c )
 {
    struct brw_compile *p = &c->func;
    struct brw_reg incoming = get_element_ud(c->reg.R0, 2);
+   struct brw_context *brw = p->brw;
    
    /* Shift so that lowest outcode bit is rightmost: 
     */
@@ -435,7 +432,11 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c )
       /* Rearrange userclip outcodes so that they come directly after
        * the fixed plane bits.
        */
-      brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14));
+      if (brw->gen == 5 || brw->is_g4x)
+         brw_AND(p, tmp, incoming, brw_imm_ud(0xff<<14));
+      else
+         brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14));
+
       brw_SHR(p, tmp, tmp, brw_imm_ud(8));
       brw_OR(p, c->reg.planemask, c->reg.planemask, tmp);