uint32_t yx_xuxv_image_mask;
};
+/**
+ * The VF can't natively handle certain types of attributes, such as GL_FIXED
+ * or most 10_10_10_2 types. These flags enable various VS workarounds to
+ * "fix" attributes at the beginning of shaders.
+ */
+#define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
+#define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
+#define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
+#define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
+#define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
/** The program key for Vertex Shaders. */
struct brw_vs_prog_key {
unsigned program_string_id;
- /*
+ /**
* Per-attribute workaround flags
+ *
+ * For each attribute, a combination of BRW_ATTRIB_WA_*.
*/
uint8_t gl_attrib_wa_flags[VERT_ATTRIB_MAX];
struct brw_sampler_prog_key_data tex;
};
+/* A big lookup table is used to figure out which and how many
+ * additional regs will inserted before the main payload in the WM
+ * program execution. These mainly relate to depth and stencil
+ * processing and the early-depth-test optimization.
+ */
+enum brw_wm_iz_bits {
+ BRW_WM_IZ_PS_KILL_ALPHATEST_BIT = 0x1,
+ BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT = 0x2,
+ BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT = 0x4,
+ BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT = 0x8,
+ BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT = 0x10,
+ BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT = 0x20,
+ BRW_WM_IZ_BIT_MAX = 0x40
+};
+
+enum brw_wm_aa_enable {
+ BRW_WM_AA_NEVER,
+ BRW_WM_AA_SOMETIMES,
+ BRW_WM_AA_ALWAYS
+};
+
/** The program key for Fragment/Pixel Shaders. */
struct brw_wm_prog_key {
+ /* Some collection of BRW_WM_IZ_* */
uint8_t iz_lookup;
bool stats_wm:1;
bool flat_shade:1;
bool clamp_fragment_color:1;
bool persample_interp:1;
bool multisample_fbo:1;
- unsigned line_aa:2;
+ enum brw_wm_aa_enable line_aa:2;
bool high_quality_derivatives:1;
bool force_dual_color_blend:1;
bool coherent_fb_fetch:1;
uint32_t swizzling[2];
};
+/** Max number of render targets in a shader */
+#define BRW_MAX_DRAW_BUFFERS 8
+
+/**
+ * Max number of binding table entries used for stream output.
+ *
+ * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
+ * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
+ *
+ * On Gen6, the size of transform feedback data is limited not by the number
+ * of components but by the number of binding table entries we set aside. We
+ * use one binding table entry for a float, one entry for a vector, and one
+ * entry per matrix column. Since the only way we can communicate our
+ * transform feedback capabilities to the client is via
+ * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
+ * worst case, in which all the varyings are floats, so we use up one binding
+ * table entry per component. Therefore we need to set aside at least 64
+ * binding table entries for use by transform feedback.
+ *
+ * Note: since we don't currently pack varyings, it is currently impossible
+ * for the client to actually use up all of these binding table entries--if
+ * all of their varyings were floats, they would run out of varying slots and
+ * fail to link. But that's a bug, so it seems prudent to go ahead and
+ * allocate the number of binding table entries we will need once the bug is
+ * fixed.
+ */
+#define BRW_MAX_SOL_BINDINGS 64
+
+/**
+ * Binding table index for the first gen6 SOL binding.
+ */
+#define BRW_GEN6_SOL_BINDING_START 0
+
+/**
+ * Stride in bytes between shader_time entries.
+ *
+ * We separate entries by a cacheline to reduce traffic between EUs writing to
+ * different entries.
+ */
+#define BRW_SHADER_TIME_STRIDE 64
+
struct brw_stage_prog_data {
struct {
/** size of our binding table. */
struct brw_image_param *image_param;
};
+static inline void
+brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
+ unsigned surf_index)
+{
+ /* A binding table index is 8 bits and the top 3 values are reserved for
+ * special things (stateless and SLM).
+ */
+ assert(surf_index <= 252);
+
+ prog_data->binding_table.size_bytes =
+ MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
+}
+
/* Data about a particular attempt to compile a program. Note that
* there can be many of these, each in a different GL state
* corresponding to a different brw_wm_prog_key struct, with different
* map, and (b) actually written by the shader. Does not include any of
* the additional varying slots defined in brw_varying_slot.
*/
- GLbitfield64 slots_valid;
+ uint64_t slots_valid;
/**
* Is this VUE map for a separate shader pipeline?
void brw_compute_vue_map(const struct gen_device_info *devinfo,
struct brw_vue_map *vue_map,
- GLbitfield64 slots_valid,
+ uint64_t slots_valid,
bool separate_shader);
void brw_compute_tess_vue_map(struct brw_vue_map *const vue_map,
- const GLbitfield64 slots_valid,
- const GLbitfield is_patch);
+ uint64_t slots_valid,
+ uint32_t is_patch);
/* brw_interpolation_map.c */
void brw_setup_vue_interpolation(struct brw_vue_map *vue_map,
projects / mesa.git / blobdiff