#pragma once
#include <stdio.h>
-#include "brw_device_info.h"
+#include "common/gen_device_info.h"
#include "main/mtypes.h"
+#include "main/macros.h"
#ifdef __cplusplus
extern "C" {
struct ra_regs;
struct nir_shader;
-struct brw_geometry_program;
+struct brw_program;
union gl_constant_value;
struct brw_compiler {
- const struct brw_device_info *devinfo;
+ const struct gen_device_info *devinfo;
struct {
struct ra_regs *regs;
* appear in *classes.
*/
int aligned_pairs_class;
- } fs_reg_sets[2];
+ } fs_reg_sets[3];
void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
bool scalar_stage[MESA_SHADER_STAGES];
struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES];
-};
-struct brw_compiler *
-brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo);
+ /**
+ * Apply workarounds for SIN and COS output range problems.
+ * This can negatively impact performance.
+ */
+ bool precise_trig;
+};
/**
* For Sandybridge, which shader w/a we need for gather quirks.
*/
enum gen6_gather_sampler_wa gen6_gather_wa[MAX_SAMPLERS];
+
+ /**
+ * Texture units that have a YUV image bound.
+ */
+ uint32_t y_u_v_image_mask;
+ uint32_t y_uv_image_mask;
+ uint32_t yx_xuxv_image_mask;
};
+/**
+ * The VF can't natively handle certain types of attributes, such as GL_FIXED
+ * or most 10_10_10_2 types. These flags enable various VS workarounds to
+ * "fix" attributes at the beginning of shaders.
+ */
+#define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
+#define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
+#define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
+#define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
+#define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
/** The program key for Vertex Shaders. */
struct brw_vs_prog_key {
unsigned program_string_id;
- /*
+ /**
* Per-attribute workaround flags
+ *
+ * For each attribute, a combination of BRW_ATTRIB_WA_*.
*/
uint8_t gl_attrib_wa_flags[VERT_ATTRIB_MAX];
/** A bitfield of per-vertex outputs written. */
uint64_t outputs_written;
+ bool quads_workaround;
+
struct brw_sampler_prog_key_data tex;
};
struct brw_sampler_prog_key_data tex;
};
+/* A big lookup table is used to figure out which and how many
+ * additional regs will inserted before the main payload in the WM
+ * program execution. These mainly relate to depth and stencil
+ * processing and the early-depth-test optimization.
+ */
+enum brw_wm_iz_bits {
+ BRW_WM_IZ_PS_KILL_ALPHATEST_BIT = 0x1,
+ BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT = 0x2,
+ BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT = 0x4,
+ BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT = 0x8,
+ BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT = 0x10,
+ BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT = 0x20,
+ BRW_WM_IZ_BIT_MAX = 0x40
+};
+
+enum brw_wm_aa_enable {
+ BRW_WM_AA_NEVER,
+ BRW_WM_AA_SOMETIMES,
+ BRW_WM_AA_ALWAYS
+};
+
/** The program key for Fragment/Pixel Shaders. */
struct brw_wm_prog_key {
+ /* Some collection of BRW_WM_IZ_* */
uint8_t iz_lookup;
bool stats_wm:1;
bool flat_shade:1;
- bool persample_shading:1;
- bool persample_2x:1;
unsigned nr_color_regions:5;
bool replicate_alpha:1;
- bool render_to_fbo:1;
bool clamp_fragment_color:1;
- bool compute_pos_offset:1;
- bool compute_sample_id:1;
- unsigned line_aa:2;
+ bool persample_interp:1;
+ bool multisample_fbo:1;
+ enum brw_wm_aa_enable line_aa:2;
bool high_quality_derivatives:1;
bool force_dual_color_blend:1;
+ bool coherent_fb_fetch:1;
uint16_t drawable_height;
uint64_t input_slots_valid;
uint32_t swizzling[2];
};
+/** Max number of render targets in a shader */
+#define BRW_MAX_DRAW_BUFFERS 8
+
+/**
+ * Max number of binding table entries used for stream output.
+ *
+ * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
+ * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
+ *
+ * On Gen6, the size of transform feedback data is limited not by the number
+ * of components but by the number of binding table entries we set aside. We
+ * use one binding table entry for a float, one entry for a vector, and one
+ * entry per matrix column. Since the only way we can communicate our
+ * transform feedback capabilities to the client is via
+ * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
+ * worst case, in which all the varyings are floats, so we use up one binding
+ * table entry per component. Therefore we need to set aside at least 64
+ * binding table entries for use by transform feedback.
+ *
+ * Note: since we don't currently pack varyings, it is currently impossible
+ * for the client to actually use up all of these binding table entries--if
+ * all of their varyings were floats, they would run out of varying slots and
+ * fail to link. But that's a bug, so it seems prudent to go ahead and
+ * allocate the number of binding table entries we will need once the bug is
+ * fixed.
+ */
+#define BRW_MAX_SOL_BINDINGS 64
+
+/**
+ * Binding table index for the first gen6 SOL binding.
+ */
+#define BRW_GEN6_SOL_BINDING_START 0
+
+/**
+ * Stride in bytes between shader_time entries.
+ *
+ * We separate entries by a cacheline to reduce traffic between EUs writing to
+ * different entries.
+ */
+#define BRW_SHADER_TIME_STRIDE 64
+
struct brw_stage_prog_data {
struct {
/** size of our binding table. */
uint32_t abo_start;
uint32_t image_start;
uint32_t shader_time_start;
+ uint32_t plane_start[3];
/** @} */
} binding_table;
struct brw_image_param *image_param;
};
+static inline void
+brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
+ unsigned surf_index)
+{
+ /* A binding table index is 8 bits and the top 3 values are reserved for
+ * special things (stateless and SLM).
+ */
+ assert(surf_index <= 252);
+
+ prog_data->binding_table.size_bytes =
+ MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
+}
+
/* Data about a particular attempt to compile a program. Note that
* there can be many of these, each in a different GL state
* corresponding to a different brw_wm_prog_key struct, with different
GLuint num_varying_inputs;
- GLuint dispatch_grf_start_reg_16;
- GLuint reg_blocks;
- GLuint reg_blocks_16;
+ uint8_t reg_blocks_0;
+ uint8_t reg_blocks_2;
+
+ uint8_t dispatch_grf_start_reg_2;
+ uint32_t prog_offset_2;
struct {
/** @{
* surface indices the WM-specific surfaces
*/
uint32_t render_target_start;
+ uint32_t render_target_read_start;
/** @} */
} binding_table;
bool computed_stencil;
bool early_fragment_tests;
- bool no_8;
+ bool post_depth_coverage;
+ bool inner_coverage;
+ bool dispatch_8;
+ bool dispatch_16;
bool dual_src_blend;
+ bool persample_dispatch;
bool uses_pos_offset;
bool uses_omask;
bool uses_kill;
bool uses_src_depth;
bool uses_src_w;
bool uses_sample_mask;
+ bool has_side_effects;
bool pulls_bary;
- uint32_t prog_offset_16;
+
+ bool contains_flat_varying;
+ bool contains_noperspective_varying;
/**
* Mask of which interpolation modes are required by the fragment shader.
*/
uint32_t barycentric_interp_modes;
+ /**
+ * Mask of which FS inputs are marked flat by the shader source. This is
+ * needed for setting up 3DSTATE_SF/SBE.
+ */
+ uint32_t flat_inputs;
+
+ /* Mapping of VUE slots to interpolation modes.
+ * Used by the Gen4-5 clip/sf/wm stages.
+ */
+ unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */
+
/**
* Map from gl_varying_slot to the position within the FS setup data
* payload where the varying's attribute vertex deltas should be delivered.
int urb_setup[VARYING_SLOT_MAX];
};
+struct brw_push_const_block {
+ unsigned dwords; /* Dword count, not reg aligned */
+ unsigned regs;
+ unsigned size; /* Bytes, register aligned */
+};
+
struct brw_cs_prog_data {
struct brw_stage_prog_data base;
GLuint dispatch_grf_start_reg_16;
unsigned local_size[3];
unsigned simd_size;
+ unsigned threads;
bool uses_barrier;
bool uses_num_work_groups;
- unsigned local_invocation_id_regs;
+ int thread_local_id_index;
+
+ struct {
+ struct brw_push_const_block cross_thread;
+ struct brw_push_const_block per_thread;
+ struct brw_push_const_block total;
+ } push;
struct {
/** @{
BRW_VARYING_SLOT_COUNT
} brw_varying_slot;
+/**
+ * We always program SF to start reading at an offset of 1 (2 varying slots)
+ * from the start of the vertex URB entry. This causes it to skip:
+ * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
+ * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
+ */
+#define BRW_SF_URB_ENTRY_READ_OFFSET 1
+
+/**
+ * Bitmask indicating which fragment shader inputs represent varyings (and
+ * hence have to be delivered to the fragment shader by the SF/SBE stage).
+ */
+#define BRW_FS_VARYING_INPUT_MASK \
+ (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
+ ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
+
/**
* Data structure recording the relationship between the gl_varying_slot enum
* and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
* map, and (b) actually written by the shader. Does not include any of
* the additional varying slots defined in brw_varying_slot.
*/
- GLbitfield64 slots_valid;
+ uint64_t slots_valid;
/**
* Is this VUE map for a separate shader pipeline?
return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
}
-void brw_compute_vue_map(const struct brw_device_info *devinfo,
+void brw_compute_vue_map(const struct gen_device_info *devinfo,
struct brw_vue_map *vue_map,
- GLbitfield64 slots_valid,
+ uint64_t slots_valid,
bool separate_shader);
void brw_compute_tess_vue_map(struct brw_vue_map *const vue_map,
- const GLbitfield64 slots_valid,
- const GLbitfield is_patch);
+ uint64_t slots_valid,
+ uint32_t is_patch);
+
+/* brw_interpolation_map.c */
+void brw_setup_vue_interpolation(struct brw_vue_map *vue_map,
+ struct nir_shader *nir,
+ struct brw_wm_prog_data *prog_data,
+ const struct gen_device_info *devinfo);
enum shader_dispatch_mode {
DISPATCH_MODE_4X1_SINGLE = 0,
GLuint urb_read_length;
GLuint total_grf;
+ uint32_t clip_distance_mask;
+ uint32_t cull_distance_mask;
+
/* Used for calculating urb partitions. In the VS, this is the size of the
* URB entry used for both input and output to the thread. In the GS, this
* is the size of the URB entry used for output.
struct brw_vue_prog_data base;
GLbitfield64 inputs_read;
+ GLbitfield64 double_inputs_read;
unsigned nr_attributes;
+ unsigned nr_attribute_slots;
bool uses_vertexid;
bool uses_instanceid;
int invocations;
- /**
- * Gen6 transform feedback enabled flag.
- */
- bool gen6_xfb_enabled;
-
/**
* Gen6: Provoking vertex convention for odd-numbered triangles
* in tristrips.
unsigned char transform_feedback_swizzles[64 /* BRW_MAX_SOL_BINDINGS */];
};
+#define DEFINE_PROG_DATA_DOWNCAST(stage) \
+static inline struct brw_##stage##_prog_data * \
+brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
+{ \
+ return (struct brw_##stage##_prog_data *) prog_data; \
+}
+DEFINE_PROG_DATA_DOWNCAST(vue)
+DEFINE_PROG_DATA_DOWNCAST(vs)
+DEFINE_PROG_DATA_DOWNCAST(tcs)
+DEFINE_PROG_DATA_DOWNCAST(tes)
+DEFINE_PROG_DATA_DOWNCAST(gs)
+DEFINE_PROG_DATA_DOWNCAST(wm)
+DEFINE_PROG_DATA_DOWNCAST(cs)
+DEFINE_PROG_DATA_DOWNCAST(ff_gs)
+DEFINE_PROG_DATA_DOWNCAST(clip)
+DEFINE_PROG_DATA_DOWNCAST(sf)
+#undef DEFINE_PROG_DATA_DOWNCAST
/** @} */
struct brw_compiler *
-brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo);
+brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo);
/**
* Compile a vertex shader.
brw_compile_tes(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const struct brw_tes_prog_key *key,
+ const struct brw_vue_map *input_vue_map,
struct brw_tes_prog_data *prog_data,
const struct nir_shader *shader,
- struct gl_shader_program *shader_prog,
+ struct gl_program *prog,
int shader_time_index,
unsigned *final_assembly_size,
char **error_str);
const struct brw_gs_prog_key *key,
struct brw_gs_prog_data *prog_data,
const struct nir_shader *shader,
- struct gl_shader_program *shader_prog,
+ struct gl_program *prog,
int shader_time_index,
unsigned *final_assembly_size,
char **error_str);
struct gl_program *prog,
int shader_time_index8,
int shader_time_index16,
- bool use_rep_send,
+ bool allow_spilling,
+ bool use_rep_send, struct brw_vue_map *vue_map,
unsigned *final_assembly_size,
char **error_str);
unsigned *final_assembly_size,
char **error_str);
+static inline uint32_t
+encode_slm_size(unsigned gen, uint32_t bytes)
+{
+ uint32_t slm_size = 0;
+
+ /* Shared Local Memory is specified as powers of two, and encoded in
+ * INTERFACE_DESCRIPTOR_DATA with the following representations:
+ *
+ * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
+ * -------------------------------------------------------------------
+ * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
+ * -------------------------------------------------------------------
+ * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
+ */
+ assert(bytes <= 64 * 1024);
+
+ if (bytes > 0) {
+ /* Shared Local Memory Size is specified as powers of two. */
+ slm_size = util_next_power_of_two(bytes);
+
+ if (gen >= 9) {
+ /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
+ slm_size = ffs(MAX2(slm_size, 1024)) - 10;
+ } else {
+ /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
+ slm_size = MAX2(slm_size, 4096) / 4096;
+ }
+ }
+
+ return slm_size;
+}
+
/**
- * Fill out local id payload for compute shader according to cs_prog_data.
+ * Return true if the given shader stage is dispatched contiguously by the
+ * relevant fixed function starting from channel 0 of the SIMD thread, which
+ * implies that the dispatch mask of a thread can be assumed to have the form
+ * '2^n - 1' for some n.
*/
-void
-brw_cs_fill_local_id_payload(const struct brw_cs_prog_data *cs_prog_data,
- void *buffer, uint32_t threads, uint32_t stride);
+static inline bool
+brw_stage_has_packed_dispatch(const struct gen_device_info *devinfo,
+ gl_shader_stage stage,
+ const struct brw_stage_prog_data *prog_data)
+{
+ /* The code below makes assumptions about the hardware's thread dispatch
+ * behavior that could be proven wrong in future generations -- Make sure
+ * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
+ * the NIR front-end before changing this assertion.
+ */
+ assert(devinfo->gen <= 9);
+
+ switch (stage) {
+ case MESA_SHADER_FRAGMENT: {
+ /* The PSD discards subspans coming in with no lit samples, which in the
+ * per-pixel shading case implies that each subspan will either be fully
+ * lit (due to the VMask being used to allow derivative computations),
+ * or not dispatched at all. In per-sample dispatch mode individual
+ * samples from the same subspan have a fixed relative location within
+ * the SIMD thread, so dispatch of unlit samples cannot be avoided in
+ * general and we should return false.
+ */
+ const struct brw_wm_prog_data *wm_prog_data =
+ (const struct brw_wm_prog_data *)prog_data;
+ return !wm_prog_data->persample_dispatch;
+ }
+ case MESA_SHADER_COMPUTE:
+ /* Compute shaders will be spawned with either a fully enabled dispatch
+ * mask or with whatever bottom/right execution mask was given to the
+ * GPGPU walker command to be used along the workgroup edges -- In both
+ * cases the dispatch mask is required to be tightly packed for our
+ * invocation index calculations to work.
+ */
+ return true;
+ default:
+ /* Most remaining fixed functions are limited to use a packed dispatch
+ * mask due to the hardware representation of the dispatch mask as a
+ * single counter representing the number of enabled channels.
+ */
+ return true;
+ }
+}
#ifdef __cplusplus
} /* extern "C" */
projects / mesa.git / blobdiff