prepare_indirect_gpgpu_walker(struct brw_context *brw)
{
GLintptr indirect_offset = brw->compute.num_work_groups_offset;
- drm_bacon_bo *bo = brw->compute.num_work_groups_bo;
+ struct brw_bo *bo = brw->compute.num_work_groups_bo;
brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMX, bo,
I915_GEM_DOMAIN_VERTEX, 0,
brw_validate_textures(brw);
+ brw_predraw_resolve_inputs(brw);
+
const int sampler_state_size = 16; /* 16 bytes */
estimated_buffer_space_needed = 512; /* batchbuffer commands */
estimated_buffer_space_needed += (BRW_MAX_TEX_UNIT *
brw->no_batch_wrap = false;
- if (drm_bacon_bufmgr_check_aperture_space(&brw->batch.bo, 1)) {
+ if (!brw_batch_has_aperture_space(brw, 0)) {
if (!fail_next) {
intel_batchbuffer_reset_to_saved(brw);
intel_batchbuffer_flush(brw);
struct brw_context *brw = brw_context(ctx);
static const GLuint indirect_group_counts[3] = { 0, 0, 0 };
struct gl_buffer_object *indirect_buffer = ctx->DispatchIndirectBuffer;
- drm_bacon_bo *bo =
+ struct brw_bo *bo =
intel_bufferobj_buffer(brw,
intel_buffer_object(indirect_buffer),
- indirect, 3 * sizeof(GLuint));
+ indirect, 3 * sizeof(GLuint), false);
brw->compute.num_work_groups_bo = bo;
brw->compute.num_work_groups_offset = indirect;