i965: upload transient indices into the same discontiguous buffer

[mesa.git] / src / mesa / drivers / dri / i965 / brw_context.h

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 7069724466ab5f4e7693eac4757849143df8657a..1e2c5a478373644fe2c7057630b9276d140759d7 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -145,7 +145,7 @@ struct brw_context;
 #define BRW_NEW_NR_VS_SURFACES         0x80000
 #define BRW_NEW_INDEX_BUFFER           0x100000
 #define BRW_NEW_VS_CONSTBUF            0x200000
-#define BRW_NEW_WM_CONSTBUF            0x200000
+#define BRW_NEW_WM_CONSTBUF            0x400000
 
 struct brw_state_flags {
    /** State update flags signalled by mesa internals */
@@ -461,8 +461,6 @@ struct brw_context
    struct {
       struct brw_state_flags dirty;
 
-      GLuint nr_color_regions;
-      struct intel_region *color_regions[MAX_DRAW_BUFFERS];
       struct intel_region *depth_region;
 
       /**
@@ -489,14 +487,6 @@ struct brw_context
       struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
       GLuint nr_enabled;
 
-#define BRW_NR_UPLOAD_BUFS 17
-#define BRW_UPLOAD_INIT_SIZE (128*1024)
-
-      struct {
-        drm_intel_bo *bo;
-        GLuint offset;
-      } upload;
-
       /* Summary of size and varying of active arrays, so we can check
        * for changes to this state:
        */
@@ -515,7 +505,6 @@ struct brw_context
       /* Updates to these fields are signaled by BRW_NEW_INDEX_BUFFER. */
       drm_intel_bo *bo;
       unsigned int offset;
-      unsigned int size;
       /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
        * avoid re-uploading the IB packet over and over if we're actually
        * referencing the same index buffer.
@@ -612,9 +601,7 @@ struct brw_context
       drm_intel_bo *const_bo;
 
       /** Binding table of pointers to surf_bo entries */
-      drm_intel_bo *bind_bo;
       uint32_t bind_bo_offset;
-      drm_intel_bo *surf_bo[BRW_VS_MAX_SURF];
       uint32_t surf_offset[BRW_VS_MAX_SURF];
       GLuint nr_surfaces;      
    } vs;
@@ -666,9 +653,7 @@ struct brw_context
       drm_intel_bo *sampler_bo;
 
       /** Binding table of pointers to surf_bo entries */
-      drm_intel_bo *bind_bo;
       uint32_t bind_bo_offset;
-      drm_intel_bo *surf_bo[BRW_WM_MAX_SURF];
       uint32_t surf_offset[BRW_WM_MAX_SURF];
 
       drm_intel_bo *prog_bo;
@@ -693,7 +678,6 @@ struct brw_context
       drm_intel_bo *depth_stencil_state_bo;
       drm_intel_bo *color_calc_state_bo;
 
-      drm_intel_bo *state_bo;
       uint32_t state_offset;
    } cc;