#include "intel_debug.h"
#include "intel_screen.h"
#include "intel_tex_obj.h"
+#include "intel_resolve_map.h"
/* Glossary:
*
BRW_STATE_META_IN_PROGRESS,
BRW_STATE_INTERPOLATION_MAP,
BRW_STATE_PUSH_CONSTANT_ALLOCATION,
+ BRW_STATE_NUM_SAMPLES,
BRW_NUM_STATE_BITS
};
#define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
#define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
#define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
+#define BRW_NEW_NUM_SAMPLES (1 << BRW_STATE_NUM_SAMPLES)
struct brw_state_flags {
/** State update flags signalled by mesa internals */
GLuint id; /**< serial no. to identify frag progs, never re-used */
};
+
+/** Subclass of Mesa compute program */
+struct brw_compute_program {
+ struct gl_compute_program program;
+ unsigned id; /**< serial no. to identify compute progs, never re-used */
+};
+
+
struct brw_shader {
struct gl_shader base;
};
/* Note: If adding fields that need anything besides a normal memcmp() for
- * comparing them, be sure to go fix the the stage-specific
- * prog_data_compare().
+ * comparing them, be sure to go fix brw_stage_prog_data_compare().
*/
struct brw_stage_prog_data {
struct {
uint32_t shader_time_start;
/** @} */
} binding_table;
+
+ GLuint nr_params; /**< number of float params/constants */
+ GLuint nr_pull_params;
+
+ /* Pointers to tracked values (only valid once
+ * _mesa_load_state_parameters has been called at runtime).
+ *
+ * These must be the last fields of the struct (see
+ * brw_stage_prog_data_compare()).
+ */
+ const float **param;
+ const float **pull_param;
};
/* Data about a particular attempt to compile a program. Note that
/** @} */
} binding_table;
- GLuint nr_params; /**< number of float params/constants */
- GLuint nr_pull_params;
bool dual_src_blend;
bool uses_pos_offset;
bool uses_omask;
* For varying slots that are not used by the FS, the value is -1.
*/
int urb_setup[VARYING_SLOT_MAX];
-
- /* Pointers to tracked values (only valid once
- * _mesa_load_state_parameters has been called at runtime).
- *
- * These must be the last fields of the struct (see
- * brw_wm_prog_data_compare()).
- */
- const float **param;
- const float **pull_param;
};
/**
GLuint curb_read_length;
GLuint urb_read_length;
GLuint total_grf;
- GLuint nr_params; /**< number of float params/constants */
- GLuint nr_pull_params; /**< number of dwords referenced by pull_param[] */
GLuint total_scratch;
/* Used for calculating urb partitions. In the VS, this is the size of the
* is the size of the URB entry used for output.
*/
GLuint urb_entry_size;
-
- /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
- const float **param;
- const float **pull_param;
};
bool include_primitive_id;
+ int invocations;
+
/**
* True if the thread should be dispatched in DUAL_INSTANCE mode, false if
* it should be dispatched in DUAL_OBJECT mode.
};
/** Number of texture sampler units */
-#define BRW_MAX_TEX_UNIT 16
+#define BRW_MAX_TEX_UNIT 32
/** Max number of render targets in a shader */
#define BRW_MAX_DRAW_BUFFERS 8
#define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
#define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
-struct brw_cached_batch_item {
- struct header *header;
- GLuint sz;
- struct brw_cached_batch_item *next;
-};
-
struct brw_vertex_buffer {
/** Buffer object containing the uploaded vertex data */
drm_intel_bo *bo;
int buffer;
- /** The corresponding Mesa vertex attribute */
- gl_vert_attrib attrib;
/** Offset of the first element within the buffer object */
unsigned int offset;
};
drm_intel_bo *workaround_bo;
bool need_workaround_flush;
- struct cached_batch_item *cached_items;
-
uint16_t emit, total;
uint16_t used, reserved_space;
uint32_t *map;
/** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
drm_intel_bo *offset_bo;
+ /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
+ bool zero_offsets;
+
/** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
GLenum primitive_mode;
*/
struct brw_stage_state
{
+ gl_shader_stage stage;
struct brw_stage_prog_data *prog_data;
/**
*/
drm_intel_bo *scratch_bo;
- /** Pull constant buffer */
- drm_intel_bo *const_bo;
-
/** Offset in the program cache to the program */
uint32_t prog_offset;
/** Upload a SAMPLER_STATE table. */
void (*upload_sampler_state_table)(struct brw_context *brw,
struct gl_program *prog,
- uint32_t sampler_count,
- uint32_t *sst_offset,
- uint32_t *sdc_offset);
+ struct brw_stage_state *stage_state);
/**
* Send the appropriate state packets to configure depth, stencil, and
drm_intel_context *hw_ctx;
+ /**
+ * Set of drm_intel_bo * that have been rendered to within this batchbuffer
+ * and would need flushing before being used from another cache domain that
+ * isn't coherent with it (i.e. the sampler).
+ */
+ struct set *render_cache;
+
/**
* Number of resets observed in the system at context creation.
*
struct {
drm_intel_bo *bo;
- GLuint offset;
- uint32_t buffer_len;
- uint32_t buffer_offset;
- char buffer[4096];
+ uint32_t next_offset;
} upload;
/**
*/
bool front_buffer_dirty;
- /**
- * Track whether front-buffer rendering is currently enabled
- *
- * A separate flag is used to track this in order to support MRT more
- * easily.
- */
- bool is_front_buffer_rendering;
-
- /**
- * Track whether front-buffer is the current read target.
- *
- * This is closely associated with is_front_buffer_rendering, but may
- * be set separately. The DRI2 fake front buffer must be referenced
- * either way.
- */
- bool is_front_buffer_reading;
-
/** Framerate throttling: @{ */
drm_intel_bo *first_post_swapbuffers_batch;
bool need_throttle;
} state;
struct brw_cache cache;
- struct brw_cached_batch_item *cached_batch_items;
/* Whether a meta-operation is in progress. */
bool meta_in_progress;
+ /* Whether the last depth/stencil packets were both NULL. */
+ bool no_depth_or_stencil;
+
struct {
struct brw_vertex_element inputs[VERT_ATTRIB_MAX];
struct brw_vertex_buffer buffers[VERT_ATTRIB_MAX];
const struct gl_geometry_program *geometry_program;
const struct gl_fragment_program *fragment_program;
- /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
- uint32_t CMD_VF_STATISTICS;
- /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
- uint32_t CMD_PIPELINE_SELECT;
+ /**
+ * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
+ * that we don't have to reemit that state every time we change FBOs.
+ */
+ int num_samples;
/**
* Platform specific constants containing the maximum number of threads
*/
struct brw_vue_map vue_map_geom_out;
- /**
- * Data structures used by all vec4 program compiles (not specific to any
- * particular program).
- */
- struct {
- struct ra_regs *regs;
-
- /**
- * Array of the ra classes for the unaligned contiguous register
- * block sizes used.
- */
- int *classes;
-
- /**
- * Mapping for register-allocated objects in *regs to the first
- * GRF for that object.
- */
- uint8_t *ra_reg_to_grf;
- } vec4;
-
struct {
struct brw_stage_state base;
struct brw_vs_prog_data *prog_data;
* Gen6. See brw_update_null_renderbuffer_surface().
*/
drm_intel_bo *multisampled_null_render_target_bo;
-
- struct {
- struct ra_regs *regs;
-
- /**
- * Array of the ra classes for the unaligned contiguous register
- * block sizes used, indexed by register size.
- */
- int classes[16];
-
- /**
- * Mapping for register-allocated objects in *regs to the first
- * GRF for that object.
- */
- uint8_t *ra_reg_to_grf;
-
- /**
- * ra class for the aligned pairs we use for PLN, which doesn't
- * appear in *classes.
- */
- int aligned_pairs_class;
- } reg_sets[2];
} wm;
struct intel_screen *intelScreen;
};
-static inline bool
-is_power_of_two(uint32_t value)
-{
- return (value & (value - 1)) == 0;
-}
-
/*======================================================================
* brw_vtbl.c
*/
unsigned *error,
void *sharedContextPrivate);
+/*======================================================================
+ * brw_misc_state.c
+ */
+GLuint brw_get_rb_for_slice(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ unsigned level, unsigned layer, bool flat);
+
+void brw_meta_updownsample(struct brw_context *brw,
+ struct intel_mipmap_tree *src,
+ struct intel_mipmap_tree *dst);
+
+void brw_meta_fbo_stencil_blit(struct brw_context *brw,
+ GLfloat srcX0, GLfloat srcY0,
+ GLfloat srcX1, GLfloat srcY1,
+ GLfloat dstX0, GLfloat dstY0,
+ GLfloat dstX1, GLfloat dstY1);
+
+void brw_meta_stencil_updownsample(struct brw_context *brw,
+ struct intel_mipmap_tree *src,
+ struct intel_mipmap_tree *dst);
/*======================================================================
* brw_misc_state.c
*/
void brw_store_register_mem64(struct brw_context *brw,
drm_intel_bo *bo, uint32_t reg, int idx);
+/** intel_batchbuffer.c */
+void brw_load_register_mem(struct brw_context *brw,
+ uint32_t reg,
+ drm_intel_bo *bo,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t offset);
+
/*======================================================================
* brw_state_dump.c
*/
/* brw_fs_reg_allocate.cpp
*/
-void brw_fs_alloc_reg_sets(struct brw_context *brw);
+void brw_fs_alloc_reg_sets(struct intel_screen *screen);
/* brw_vec4_reg_allocate.cpp */
-void brw_vec4_alloc_reg_set(struct brw_context *brw);
+void brw_vec4_alloc_reg_set(struct intel_screen *screen);
/* brw_disasm.c */
-int brw_disasm (FILE *file, struct brw_instruction *inst, int gen);
+int brw_disassemble_inst(FILE *file, struct brw_instruction *inst,
+ int gen, bool is_compacted);
/* brw_vs.c */
gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
unsigned brw_get_vertex_surface_type(struct brw_context *brw,
const struct gl_client_array *glarray);
unsigned brw_get_index_type(GLenum type);
+void brw_prepare_vertices(struct brw_context *brw);
/* brw_wm_surface_state.c */
void brw_init_surface_formats(struct brw_context *brw);
struct brw_stage_prog_data *prog_data);
/* brw_surface_formats.c */
-bool brw_is_hiz_depth_format(struct brw_context *ctx, gl_format format);
+bool brw_is_hiz_depth_format(struct brw_context *ctx, mesa_format format);
bool brw_render_target_supported(struct brw_context *brw,
struct gl_renderbuffer *rb);
+uint32_t brw_depth_format(struct brw_context *brw, mesa_format format);
/* brw_performance_monitor.c */
void brw_init_performance_monitors(struct brw_context *brw);
void brw_perf_monitor_new_batch(struct brw_context *brw);
void brw_perf_monitor_finish_batch(struct brw_context *brw);
+/* intel_buffer_objects.c */
+int brw_bo_map(struct brw_context *brw, drm_intel_bo *bo, int write_enable,
+ const char *bo_name);
+int brw_bo_map_gtt(struct brw_context *brw, drm_intel_bo *bo,
+ const char *bo_name);
+
/* intel_extensions.c */
extern void intelInitExtensions(struct gl_context *ctx);
GLuint index,
GLfloat *result);
+/* gen8_multisample_state.c */
+void gen8_emit_3dstate_multisample(struct brw_context *brw, unsigned num_samp);
+void gen8_emit_3dstate_sample_pattern(struct brw_context *brw);
+
/* gen7_urb.c */
void
gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
bool brw_do_cubemap_normalize(struct exec_list *instructions);
bool brw_lower_texture_gradients(struct brw_context *brw,
struct exec_list *instructions);
-bool brw_do_lower_offset_arrays(struct exec_list *instructions);
bool brw_do_lower_unnormalized_offset(struct exec_list *instructions);
struct opcode_desc {
extern const struct opcode_desc opcode_descs[128];
extern const char * const conditional_modifier[16];
-extern const char * const reg_encoding[8];
void
brw_emit_depthbuffer(struct brw_context *brw);
bool hiz, bool separate_stencil,
uint32_t width, uint32_t height,
uint32_t tile_x, uint32_t tile_y);
+void
+gen8_emit_depth_stencil_hiz(struct brw_context *brw,
+ struct intel_mipmap_tree *depth_mt,
+ uint32_t depth_offset, uint32_t depthbuffer_format,
+ uint32_t depth_surface_type,
+ struct intel_mipmap_tree *stencil_mt,
+ bool hiz, bool separate_stencil,
+ uint32_t width, uint32_t height,
+ uint32_t tile_x, uint32_t tile_y);
+
+void gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
+ unsigned int level, unsigned int layer, enum gen6_hiz_op op);
extern const GLuint prim_to_hw_prim[GL_TRIANGLE_STRIP_ADJACENCY+1];
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