i965: Delete brw_do_cubemap_normalize

[mesa.git] / src / mesa / drivers / dri / i965 / brw_context.h

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 20ebebef117d13a31fcfb5e605396e0d2301f5d7..288ef3a20664a8d7f87e7300cb364291cb54eb35 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -363,9 +363,6 @@ struct brw_ff_gs_prog_data {
 /** Number of texture sampler units */
 #define BRW_MAX_TEX_UNIT 32
 
-/** Max number of render targets in a shader */
-#define BRW_MAX_DRAW_BUFFERS 8
-
 /** Max number of UBOs in a shader */
 #define BRW_MAX_UBO 14
 
@@ -390,14 +387,6 @@ struct brw_ff_gs_prog_data {
                             2 + /* shader time, pull constants */       \
                             1 /* cs num work groups */)
 
-/**
- * Stride in bytes between shader_time entries.
- *
- * We separate entries by a cacheline to reduce traffic between EUs writing to
- * different entries.
- */
-#define SHADER_TIME_STRIDE 64
-
 struct brw_cache {
    struct brw_context *brw;
 
@@ -1551,17 +1540,6 @@ brw_program_const(const struct gl_program *p)
    return (const struct brw_program *) p;
 }
 
-/**
- * Pre-gen6, the register file of the EUs was shared between threads,
- * and each thread used some subset allocated on a 16-register block
- * granularity.  The unit states wanted these block counts.
- */
-static inline int
-brw_register_blocks(int reg_count)
-{
-   return ALIGN(reg_count, 16) / 16 - 1;
-}
-
 static inline uint32_t
 brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
                  uint32_t prog_offset)
@@ -1580,8 +1558,6 @@ brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
    return brw->cache.bo->offset64 + prog_offset;
 }
 
-bool brw_do_cubemap_normalize(struct exec_list *instructions);
-
 static inline bool
 brw_depth_writes_enabled(const struct brw_context *brw)
 {