i965: Delete brw_do_cubemap_normalize

[mesa.git] / src / mesa / drivers / dri / i965 / brw_context.h

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index aa938b6e1ef9ba3e74485dcd1dbca64a6fae5c00..288ef3a20664a8d7f87e7300cb364291cb54eb35 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -363,9 +363,6 @@ struct brw_ff_gs_prog_data {
 /** Number of texture sampler units */
 #define BRW_MAX_TEX_UNIT 32
 
-/** Max number of render targets in a shader */
-#define BRW_MAX_DRAW_BUFFERS 8
-
 /** Max number of UBOs in a shader */
 #define BRW_MAX_UBO 14
 
@@ -378,31 +375,6 @@ struct brw_ff_gs_prog_data {
 /** Max number of image uniforms in a shader */
 #define BRW_MAX_IMAGES 32
 
-/**
- * Max number of binding table entries used for stream output.
- *
- * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
- * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
- *
- * On Gen6, the size of transform feedback data is limited not by the number
- * of components but by the number of binding table entries we set aside.  We
- * use one binding table entry for a float, one entry for a vector, and one
- * entry per matrix column.  Since the only way we can communicate our
- * transform feedback capabilities to the client is via
- * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
- * worst case, in which all the varyings are floats, so we use up one binding
- * table entry per component.  Therefore we need to set aside at least 64
- * binding table entries for use by transform feedback.
- *
- * Note: since we don't currently pack varyings, it is currently impossible
- * for the client to actually use up all of these binding table entries--if
- * all of their varyings were floats, they would run out of varying slots and
- * fail to link.  But that's a bug, so it seems prudent to go ahead and
- * allocate the number of binding table entries we will need once the bug is
- * fixed.
- */
-#define BRW_MAX_SOL_BINDINGS 64
-
 /** Maximum number of actual buffers used for stream output */
 #define BRW_MAX_SOL_BUFFERS 4
 
@@ -415,16 +387,6 @@ struct brw_ff_gs_prog_data {
                             2 + /* shader time, pull constants */       \
                             1 /* cs num work groups */)
 
-#define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
-
-/**
- * Stride in bytes between shader_time entries.
- *
- * We separate entries by a cacheline to reduce traffic between EUs writing to
- * different entries.
- */
-#define SHADER_TIME_STRIDE 64
-
 struct brw_cache {
    struct brw_context *brw;
 
@@ -522,8 +484,6 @@ struct intel_batchbuffer {
    } saved;
 };
 
-#define MAX_GS_INPUT_VERTICES 6
-
 #define BRW_MAX_XFB_STREAMS 4
 
 struct brw_transform_feedback_object {
@@ -1580,17 +1540,6 @@ brw_program_const(const struct gl_program *p)
    return (const struct brw_program *) p;
 }
 
-/**
- * Pre-gen6, the register file of the EUs was shared between threads,
- * and each thread used some subset allocated on a 16-register block
- * granularity.  The unit states wanted these block counts.
- */
-static inline int
-brw_register_blocks(int reg_count)
-{
-   return ALIGN(reg_count, 16) / 16 - 1;
-}
-
 static inline uint32_t
 brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
                  uint32_t prog_offset)
@@ -1609,8 +1558,6 @@ brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
    return brw->cache.bo->offset64 + prog_offset;
 }
 
-bool brw_do_cubemap_normalize(struct exec_list *instructions);
-
 static inline bool
 brw_depth_writes_enabled(const struct brw_context *brw)
 {