i965: Clean up error handling for context creation.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_context.h

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 988e9fbf656d95a52b1e57770ab0beedbde969a7..28ae261a68ae955551903bc90d720616369536d3 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -128,6 +128,7 @@ struct brw_vs_prog_key;
 struct brw_vec4_prog_key;
 struct brw_wm_prog_key;
 struct brw_wm_prog_data;
+struct brw_perf_bo_layout;
 
 enum brw_state_id {
    BRW_STATE_URB_FENCE,
@@ -314,7 +315,7 @@ struct brw_shader {
  */
 struct brw_wm_prog_data {
    GLuint curb_read_length;
-   GLuint urb_read_length;
+   GLuint num_varying_inputs;
 
    GLuint first_curbe_grf;
    GLuint first_curbe_grf_16;
@@ -436,7 +437,16 @@ static inline GLuint brw_varying_to_offset(struct brw_vue_map *vue_map,
 }
 
 void brw_compute_vue_map(struct brw_context *brw, struct brw_vue_map *vue_map,
-                         GLbitfield64 slots_valid, bool userclip_active);
+                         GLbitfield64 slots_valid);
+
+
+/**
+ * Bitmask indicating which fragment shader inputs represent varyings (and
+ * hence have to be delivered to the fragment shader by the SF/SBE stage).
+ */
+#define BRW_FS_VARYING_INPUT_MASK \
+   (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
+    ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
 
 
 /*
@@ -478,6 +488,16 @@ struct brw_sf_prog_data {
    GLuint urb_entry_size;
 };
 
+
+/**
+ * We always program SF to start reading at an offset of 1 (2 varying slots)
+ * from the start of the vertex URB entry.  This causes it to skip:
+ * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
+ * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
+ */
+#define BRW_SF_URB_ENTRY_READ_OFFSET 1
+
+
 struct brw_clip_prog_data {
    GLuint curb_read_length;    /* user planes? */
    GLuint clip_mode;
@@ -569,6 +589,8 @@ struct brw_gs_prog_data
     * Ignored if control_data_header_size is 0.
     */
    unsigned control_data_format;
+
+   bool include_primitive_id;
 };
 
 /** Number of texture sampler units */
@@ -638,6 +660,13 @@ struct brw_gs_prog_data
  *    |   . |     .                   |
  *    |   : |     :                   |
  *    |  36 | UBO 11                  |
+ *    |-----|-------------------------|
+ *    |  37 | Shader time buffer      |
+ *    |-----|-------------------------|
+ *    |  38 | Gather texture 0        |
+ *    |   . |     .                   |
+ *    |   : |     :                   |
+ *    |  53 | Gather texture 15       |
  *    +-------------------------------+
  *
  * Our VS (and Gen7 GS) binding tables are programmed as follows:
@@ -654,6 +683,13 @@ struct brw_gs_prog_data
  *    |   . |     .                   |
  *    |   : |     :                   |
  *    |  28 | UBO 11                  |
+ *    |-----|-------------------------|
+ *    |  29 | Shader time buffer      |
+ *    |-----|-------------------------|
+ *    |  30 | Gather texture 0        |
+ *    |   . |     .                   |
+ *    |   : |     :                   |
+ *    |  45 | Gather texture 15       |
  *    +-------------------------------+
  *
  * Our (gen6) GS binding tables are programmed as follows:
@@ -670,14 +706,16 @@ struct brw_gs_prog_data
 #define SURF_INDEX_TEXTURE(t)        (BRW_MAX_DRAW_BUFFERS + 2 + (t))
 #define SURF_INDEX_WM_UBO(u)         (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u)
 #define SURF_INDEX_WM_SHADER_TIME    (SURF_INDEX_WM_UBO(12))
+#define SURF_INDEX_GATHER_TEXTURE(t) (SURF_INDEX_WM_SHADER_TIME + 1 + (t))
 /** Maximum size of the binding table. */
-#define BRW_MAX_WM_SURFACES          (SURF_INDEX_WM_SHADER_TIME + 1)
+#define BRW_MAX_WM_SURFACES          (SURF_INDEX_GATHER_TEXTURE(BRW_MAX_TEX_UNIT))
 
 #define SURF_INDEX_VEC4_CONST_BUFFER (0)
 #define SURF_INDEX_VEC4_TEXTURE(t)   (SURF_INDEX_VEC4_CONST_BUFFER + 1 + (t))
 #define SURF_INDEX_VEC4_UBO(u)       (SURF_INDEX_VEC4_TEXTURE(BRW_MAX_TEX_UNIT) + u)
 #define SURF_INDEX_VEC4_SHADER_TIME  (SURF_INDEX_VEC4_UBO(12))
-#define BRW_MAX_VEC4_SURFACES        (SURF_INDEX_VEC4_SHADER_TIME + 1)
+#define SURF_INDEX_VEC4_GATHER_TEXTURE(t)   (SURF_INDEX_VEC4_SHADER_TIME + 1 + (t))
+#define BRW_MAX_VEC4_SURFACES        (SURF_INDEX_VEC4_GATHER_TEXTURE(BRW_MAX_TEX_UNIT))
 
 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
 #define BRW_MAX_GEN6_GS_SURFACES       SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
@@ -787,6 +825,8 @@ enum shader_time_shader_type {
 #define CACHE_NEW_CC_VP                  (1<<BRW_CC_VP)
 #define CACHE_NEW_CC_UNIT                (1<<BRW_CC_UNIT)
 #define CACHE_NEW_WM_PROG                (1<<BRW_WM_PROG)
+#define CACHE_NEW_BLORP_BLIT_PROG        (1<<BRW_BLORP_BLIT_PROG)
+#define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
 #define CACHE_NEW_SAMPLER                (1<<BRW_SAMPLER)
 #define CACHE_NEW_WM_UNIT                (1<<BRW_WM_UNIT)
 #define CACHE_NEW_SF_PROG                (1<<BRW_SF_PROG)
@@ -888,7 +928,8 @@ struct brw_context
 
       void (*update_texture_surface)(struct gl_context *ctx,
                                      unsigned unit,
-                                     uint32_t *surf_offset);
+                                     uint32_t *surf_offset,
+                                     bool for_gather);
       void (*update_renderbuffer_surface)(struct brw_context *brw,
                                          struct gl_renderbuffer *rb,
                                          bool layered,
@@ -981,6 +1022,7 @@ struct brw_context
    bool always_flush_cache;
    bool disable_throttling;
    bool precompile;
+   bool disable_derivative_optimization;
 
    driOptionCache optionCache;
    /** @} */
@@ -1258,10 +1300,11 @@ struct brw_context
       struct {
          struct ra_regs *regs;
 
-         /** Array of the ra classes for the unaligned contiguous
-          * register block sizes used.
+         /**
+          * Array of the ra classes for the unaligned contiguous register
+          * block sizes used, indexed by register size.
           */
-         int *classes;
+         int classes[16];
 
          /**
           * Mapping for register-allocated objects in *regs to the first
@@ -1290,6 +1333,16 @@ struct brw_context
       bool begin_emitted;
    } query;
 
+   struct {
+      /* A map describing which counters are stored at a particular 32-bit
+       * offset in the buffer object.
+       */
+      const struct brw_perf_bo_layout *bo_layout;
+
+      /* Number of 32-bit entries in the buffer object. */
+      int entries_in_bo;
+   } perfmon;
+
    int num_atoms;
    const struct brw_tracked_state **atoms;
 
@@ -1357,7 +1410,7 @@ void brwInitVtbl( struct brw_context *brw );
 /*======================================================================
  * brw_context.c
  */
-bool brwCreateContext(int api,
+bool brwCreateContext(gl_api api,
                      const struct gl_config *mesaVis,
                      __DRIcontext *driContextPriv,
                       unsigned major_version,
@@ -1462,6 +1515,9 @@ bool brw_is_hiz_depth_format(struct brw_context *ctx, gl_format format);
 bool brw_render_target_supported(struct brw_context *brw,
                                  struct gl_renderbuffer *rb);
 
+/* brw_performance_monitor.c */
+void brw_init_performance_monitors(struct brw_context *brw);
+
 /* gen6_sol.c */
 void
 brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
@@ -1619,7 +1675,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
                             uint32_t width, uint32_t height,
                             uint32_t tile_x, uint32_t tile_y);
 
-extern const GLuint prim_to_hw_prim[GL_POLYGON+1];
+extern const GLuint prim_to_hw_prim[GL_TRIANGLE_STRIP_ADJACENCY+1];
 
 void
 brw_setup_vec4_key_clip_info(struct brw_context *brw,