struct brw_context;
struct brw_instruction;
struct brw_vs_prog_key;
+struct brw_vec4_prog_key;
struct brw_wm_prog_key;
struct brw_wm_prog_data;
+struct brw_perf_bo_layout;
enum brw_state_id {
BRW_STATE_URB_FENCE,
BRW_STATE_FRAGMENT_PROGRAM,
+ BRW_STATE_GEOMETRY_PROGRAM,
BRW_STATE_VERTEX_PROGRAM,
BRW_STATE_CURBE_OFFSETS,
BRW_STATE_REDUCED_PRIMITIVE,
BRW_STATE_BATCH,
BRW_STATE_INDEX_BUFFER,
BRW_STATE_VS_CONSTBUF,
+ BRW_STATE_GS_CONSTBUF,
BRW_STATE_PROGRAM_CACHE,
BRW_STATE_STATE_BASE_ADDRESS,
- BRW_STATE_SOL_INDICES,
+ BRW_STATE_VUE_MAP_VS,
BRW_STATE_VUE_MAP_GEOM_OUT,
BRW_STATE_TRANSFORM_FEEDBACK,
BRW_STATE_RASTERIZER_DISCARD,
BRW_STATE_STATS_WM,
- BRW_STATE_UNIFORM_BUFFER
+ BRW_STATE_UNIFORM_BUFFER,
+ BRW_STATE_META_IN_PROGRESS,
+ BRW_STATE_INTERPOLATION_MAP,
+ BRW_STATE_PUSH_CONSTANT_ALLOCATION,
+ BRW_NUM_STATE_BITS
};
#define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
#define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
+#define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
#define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
#define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
#define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
/** \see brw.state.depth_region */
#define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
#define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
+#define BRW_NEW_GS_CONSTBUF (1 << BRW_STATE_GS_CONSTBUF)
#define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
#define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
-#define BRW_NEW_SOL_INDICES (1 << BRW_STATE_SOL_INDICES)
+#define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
#define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
#define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
#define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
#define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
#define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
+#define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
+#define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
+#define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
struct brw_state_flags {
/** State update flags signalled by mesa internals */
};
+/** Subclass of Mesa geometry program */
+struct brw_geometry_program {
+ struct gl_geometry_program program;
+ unsigned id; /**< serial no. to identify geom progs, never re-used */
+};
+
+
/** Subclass of Mesa fragment program */
struct brw_fragment_program {
struct gl_fragment_program program;
*/
struct brw_wm_prog_data {
GLuint curb_read_length;
- GLuint urb_read_length;
+ GLuint num_varying_inputs;
GLuint first_curbe_grf;
GLuint first_curbe_grf_16;
GLuint reg_blocks_16;
GLuint total_scratch;
+ unsigned binding_table_size;
+
GLuint nr_params; /**< number of float params/constants */
GLuint nr_pull_params;
bool dual_src_blend;
*/
uint32_t barycentric_interp_modes;
+ /**
+ * Map from gl_varying_slot to the position within the FS setup data
+ * payload where the varying's attribute vertex deltas should be delivered.
+ * For varying slots that are not used by the FS, the value is -1.
+ */
+ int urb_setup[VARYING_SLOT_MAX];
+
/* Pointers to tracked values (only valid once
* _mesa_load_state_parameters has been called at runtime).
*
typedef enum
{
BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX,
- BRW_VARYING_SLOT_POS_DUPLICATE,
BRW_VARYING_SLOT_PAD,
/**
* Technically this is not a varying but just a placeholder that
}
void brw_compute_vue_map(struct brw_context *brw, struct brw_vue_map *vue_map,
- GLbitfield64 slots_valid, bool userclip_active);
+ GLbitfield64 slots_valid);
+
+
+/**
+ * Bitmask indicating which fragment shader inputs represent varyings (and
+ * hence have to be delivered to the fragment shader by the SF/SBE stage).
+ */
+#define BRW_FS_VARYING_INPUT_MASK \
+ (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
+ ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
+
+
+/*
+ * Mapping of VUE map slots to interpolation modes.
+ */
+struct interpolation_mode_map {
+ unsigned char mode[BRW_VARYING_SLOT_COUNT];
+};
+
+static inline bool brw_any_flat_varyings(struct interpolation_mode_map *map)
+{
+ for (int i = 0; i < BRW_VARYING_SLOT_COUNT; i++)
+ if (map->mode[i] == INTERP_QUALIFIER_FLAT)
+ return true;
+
+ return false;
+}
+
+static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map *map)
+{
+ for (int i = 0; i < BRW_VARYING_SLOT_COUNT; i++)
+ if (map->mode[i] == INTERP_QUALIFIER_NOPERSPECTIVE)
+ return true;
+
+ return false;
+}
struct brw_sf_prog_data {
GLuint urb_entry_size;
};
+
+/**
+ * We always program SF to start reading at an offset of 1 (2 varying slots)
+ * from the start of the vertex URB entry. This causes it to skip:
+ * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
+ * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
+ */
+#define BRW_SF_URB_ENTRY_READ_OFFSET 1
+
+
struct brw_clip_prog_data {
GLuint curb_read_length; /* user planes? */
GLuint clip_mode;
GLuint total_grf;
};
-struct brw_gs_prog_data {
+struct brw_ff_gs_prog_data {
GLuint urb_read_length;
GLuint total_grf;
struct brw_vec4_prog_data {
struct brw_vue_map vue_map;
+ /**
+ * Register where the thread expects to find input data from the URB
+ * (typically uniforms, followed by per-vertex inputs).
+ */
+ unsigned dispatch_grf_start_reg;
+
GLuint curb_read_length;
GLuint urb_read_length;
GLuint total_grf;
*/
GLuint urb_entry_size;
- int num_surfaces;
+ unsigned binding_table_size;
/* These pointers must appear last. See brw_vec4_prog_data_compare(). */
const float **param;
bool uses_vertexid;
};
+
+/* Note: brw_gs_prog_data_compare() must be updated when adding fields to
+ * this struct!
+ */
+struct brw_gs_prog_data
+{
+ struct brw_vec4_prog_data base;
+
+ /**
+ * Size of an output vertex, measured in HWORDS (32 bytes).
+ */
+ unsigned output_vertex_size_hwords;
+
+ unsigned output_topology;
+
+ /**
+ * Size of the control data (cut bits or StreamID bits), in hwords (32
+ * bytes). 0 if there is no control data.
+ */
+ unsigned control_data_header_size_hwords;
+
+ /**
+ * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
+ * if the control data is StreamID bits, or
+ * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
+ * Ignored if control_data_header_size is 0.
+ */
+ unsigned control_data_format;
+
+ bool include_primitive_id;
+};
+
/** Number of texture sampler units */
#define BRW_MAX_TEX_UNIT 16
* | . | . |
* | : | : |
* | 36 | UBO 11 |
+ * |-----|-------------------------|
+ * | 37 | Shader time buffer |
+ * |-----|-------------------------|
+ * | 38 | Gather texture 0 |
+ * | . | . |
+ * | : | : |
+ * | 53 | Gather texture 15 |
* +-------------------------------+
*
- * Our VS binding tables are programmed as follows:
+ * Our VS (and Gen7 GS) binding tables are programmed as follows:
*
* +-----+-------------------------+
- * | 0 | VS Pull Constant Buffer |
+ * | 0 | Pull Constant Buffer |
* +-----+-------------------------+
* | 1 | Texture 0 |
* | . | . |
* | . | . |
* | : | : |
* | 28 | UBO 11 |
+ * |-----|-------------------------|
+ * | 29 | Shader time buffer |
+ * |-----|-------------------------|
+ * | 30 | Gather texture 0 |
+ * | . | . |
+ * | : | : |
+ * | 45 | Gather texture 15 |
* +-------------------------------+
*
* Our (gen6) GS binding tables are programmed as follows:
* | : | : |
* | 63 | SOL Binding 63 |
* +-----+-------------------------+
- *
- * Note that nothing actually uses the SURF_INDEX_DRAW macro, so it has to be
- * the identity function or things will break. We do want to keep draw buffers
- * first so we can use headerless render target writes for RT 0.
*/
#define SURF_INDEX_DRAW(d) (d)
#define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
#define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
#define SURF_INDEX_WM_UBO(u) (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u)
#define SURF_INDEX_WM_SHADER_TIME (SURF_INDEX_WM_UBO(12))
+#define SURF_INDEX_GATHER_TEXTURE(t) (SURF_INDEX_WM_SHADER_TIME + 1 + (t))
/** Maximum size of the binding table. */
-#define BRW_MAX_WM_SURFACES (SURF_INDEX_WM_SHADER_TIME + 1)
+#define BRW_MAX_WM_SURFACES (SURF_INDEX_GATHER_TEXTURE(BRW_MAX_TEX_UNIT))
-#define SURF_INDEX_VERT_CONST_BUFFER (0)
-#define SURF_INDEX_VS_TEXTURE(t) (SURF_INDEX_VERT_CONST_BUFFER + 1 + (t))
-#define SURF_INDEX_VS_UBO(u) (SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT) + u)
-#define SURF_INDEX_VS_SHADER_TIME (SURF_INDEX_VS_UBO(12))
-#define BRW_MAX_VS_SURFACES (SURF_INDEX_VS_SHADER_TIME + 1)
+#define SURF_INDEX_VEC4_CONST_BUFFER (0)
+#define SURF_INDEX_VEC4_TEXTURE(t) (SURF_INDEX_VEC4_CONST_BUFFER + 1 + (t))
+#define SURF_INDEX_VEC4_UBO(u) (SURF_INDEX_VEC4_TEXTURE(BRW_MAX_TEX_UNIT) + u)
+#define SURF_INDEX_VEC4_SHADER_TIME (SURF_INDEX_VEC4_UBO(12))
+#define SURF_INDEX_VEC4_GATHER_TEXTURE(t) (SURF_INDEX_VEC4_SHADER_TIME + 1 + (t))
+#define BRW_MAX_VEC4_SURFACES (SURF_INDEX_VEC4_GATHER_TEXTURE(BRW_MAX_TEX_UNIT))
-#define SURF_INDEX_SOL_BINDING(t) ((t))
-#define BRW_MAX_GS_SURFACES SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
+#define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
+#define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
/**
* Stride in bytes between shader_time entries.
#define SHADER_TIME_STRIDE 64
enum brw_cache_id {
- BRW_BLEND_STATE,
- BRW_DEPTH_STENCIL_STATE,
- BRW_COLOR_CALC_STATE,
BRW_CC_VP,
BRW_CC_UNIT,
BRW_WM_PROG,
BRW_BLORP_BLIT_PROG,
- BRW_BLORP_CLEAR_PROG,
+ BRW_BLORP_CONST_COLOR_PROG,
BRW_SAMPLER,
BRW_WM_UNIT,
BRW_SF_PROG,
BRW_SF_UNIT, /* scissor state on gen6 */
BRW_VS_UNIT,
BRW_VS_PROG,
- BRW_GS_UNIT,
+ BRW_FF_GS_UNIT,
+ BRW_FF_GS_PROG,
BRW_GS_PROG,
BRW_CLIP_VP,
BRW_CLIP_UNIT,
/* Flags for brw->state.cache.
*/
-#define CACHE_NEW_BLEND_STATE (1<<BRW_BLEND_STATE)
-#define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
-#define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE)
#define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
#define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
#define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
+#define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
+#define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
#define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
#define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
#define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
#define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
#define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
#define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
-#define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
+#define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
+#define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
#define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
#define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
#define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
struct brw_cached_batch_item *next;
};
-
-
-/* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
- * be easier if C allowed arrays of packed elements?
- */
-#define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
-
struct brw_vertex_buffer {
/** Buffer object containing the uploaded vertex data */
drm_intel_bo *bo;
/**
- * brw_context is derived from intel_context.
+ * Data shared between brw_context::vs and brw_context::gs
+ */
+struct brw_stage_state
+{
+ /**
+ * Optional scratch buffer used to store spilled register values and
+ * variably-indexed GRF arrays.
+ */
+ drm_intel_bo *scratch_bo;
+
+ /** Pull constant buffer */
+ drm_intel_bo *const_bo;
+
+ /** Offset in the program cache to the program */
+ uint32_t prog_offset;
+
+ /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
+ uint32_t state_offset;
+
+ uint32_t push_const_offset; /* Offset in the batchbuffer */
+ int push_const_size; /* in 256-bit register increments */
+
+ /* Binding table: pointers to SURFACE_STATE entries. */
+ uint32_t bind_bo_offset;
+ uint32_t surf_offset[BRW_MAX_WM_SURFACES];
+
+ /** SAMPLER_STATE count and table offset */
+ uint32_t sampler_count;
+ uint32_t sampler_offset;
+
+ /** Offsets in the batch to sampler default colors (texture border color) */
+ uint32_t sdc_offset[BRW_MAX_TEX_UNIT];
+};
+
+
+/**
+ * brw_context is derived from gl_context.
*/
struct brw_context
{
- struct intel_context intel; /**< base class, must be first field */
+ struct gl_context ctx; /**< base class, must be first field */
+
+ struct
+ {
+ void (*destroy) (struct brw_context * brw);
+ void (*finish_batch) (struct brw_context * brw);
+ void (*new_batch) (struct brw_context * brw);
+
+ void (*update_texture_surface)(struct gl_context *ctx,
+ unsigned unit,
+ uint32_t *surf_offset,
+ bool for_gather);
+ void (*update_renderbuffer_surface)(struct brw_context *brw,
+ struct gl_renderbuffer *rb,
+ bool layered,
+ unsigned unit);
+ void (*update_null_renderbuffer_surface)(struct brw_context *brw,
+ unsigned unit);
+ void (*create_constant_surface)(struct brw_context *brw,
+ drm_intel_bo *bo,
+ uint32_t offset,
+ uint32_t size,
+ uint32_t *out_offset,
+ bool dword_pitch);
+
+ /** Upload a SAMPLER_STATE table. */
+ void (*upload_sampler_state_table)(struct brw_context *brw,
+ struct gl_program *prog,
+ uint32_t sampler_count,
+ uint32_t *sst_offset,
+ uint32_t *sdc_offset);
+
+ /**
+ * Send the appropriate state packets to configure depth, stencil, and
+ * HiZ buffers (i965+ only)
+ */
+ void (*emit_depth_stencil_hiz)(struct brw_context *brw,
+ struct intel_mipmap_tree *depth_mt,
+ uint32_t depth_offset,
+ uint32_t depthbuffer_format,
+ uint32_t depth_surface_type,
+ struct intel_mipmap_tree *stencil_mt,
+ bool hiz, bool separate_stencil,
+ uint32_t width, uint32_t height,
+ uint32_t tile_x, uint32_t tile_y);
+
+ } vtbl;
+
+ dri_bufmgr *bufmgr;
+
+ drm_intel_context *hw_ctx;
+
+ struct intel_batchbuffer batch;
+ bool no_batch_wrap;
+
+ struct {
+ drm_intel_bo *bo;
+ GLuint offset;
+ uint32_t buffer_len;
+ uint32_t buffer_offset;
+ char buffer[4096];
+ } upload;
+
+ /**
+ * Set if rendering has occured to the drawable's front buffer.
+ *
+ * This is used in the DRI2 case to detect that glFlush should also copy
+ * the contents of the fake front buffer to the real front buffer.
+ */
+ bool front_buffer_dirty;
+
+ /**
+ * Track whether front-buffer rendering is currently enabled
+ *
+ * A separate flag is used to track this in order to support MRT more
+ * easily.
+ */
+ bool is_front_buffer_rendering;
+
+ /**
+ * Track whether front-buffer is the current read target.
+ *
+ * This is closely associated with is_front_buffer_rendering, but may
+ * be set separately. The DRI2 fake front buffer must be referenced
+ * either way.
+ */
+ bool is_front_buffer_reading;
+
+ /** Framerate throttling: @{ */
+ drm_intel_bo *first_post_swapbuffers_batch;
+ bool need_throttle;
+ /** @} */
+
+ GLuint stats_wm;
+
+ /**
+ * drirc options:
+ * @{
+ */
+ bool no_rast;
+ bool always_flush_batch;
+ bool always_flush_cache;
+ bool disable_throttling;
+ bool precompile;
+ bool disable_derivative_optimization;
+
+ driOptionCache optionCache;
+ /** @} */
+
GLuint primitive; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
+ GLenum reduced_primitive;
+
+ /**
+ * Set if we're either a debug context or the INTEL_DEBUG=perf environment
+ * variable is set, this is the flag indicating to do expensive work that
+ * might lead to a perf_debug() call.
+ */
+ bool perf_debug;
+
+ uint32_t max_gtt_map_object_size;
+
bool emit_state_always;
+
+ int gen;
+ int gt;
+
+ bool is_g4x;
+ bool is_baytrail;
+ bool is_haswell;
+
+ bool has_hiz;
+ bool has_separate_stencil;
+ bool must_use_separate_stencil;
+ bool has_llc;
+ bool has_swizzling;
bool has_surface_tile_offset;
bool has_compr4;
bool has_negative_rhw_bug;
bool has_aa_line_parameters;
bool has_pln;
- bool precompile;
/**
* Some versions of Gen hardware don't do centroid interpolation correctly
*/
bool needs_unlit_centroid_workaround;
+ GLuint NewGLState;
struct {
struct brw_state_flags dirty;
} state;
struct brw_cache cache;
struct brw_cached_batch_item *cached_batch_items;
+ /* Whether a meta-operation is in progress. */
+ bool meta_in_progress;
+
struct {
struct brw_vertex_element inputs[VERT_ATTRIB_MAX];
struct brw_vertex_buffer buffers[VERT_ATTRIB_MAX];
/* Active vertex program:
*/
const struct gl_vertex_program *vertex_program;
+ const struct gl_geometry_program *geometry_program;
const struct gl_fragment_program *fragment_program;
/* hw-dependent 3DSTATE_VF_STATISTICS opcode */
bool constrained;
+ GLuint min_vs_entries; /* Minimum number of VS entries */
GLuint max_vs_entries; /* Maximum number of VS entries */
GLuint max_gs_entries; /* Maximum number of GS entries */
GLuint last_bufsz;
} curbe;
- /** SAMPLER_STATE count and offset */
- struct {
- GLuint count;
- uint32_t offset;
- } sampler;
+ /**
+ * Layout of vertex data exiting the vertex shader.
+ *
+ * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
+ */
+ struct brw_vue_map vue_map_vs;
/**
* Layout of vertex data exiting the geometry portion of the pipleine.
*/
struct brw_vue_map vue_map_geom_out;
+ /**
+ * Data structures used by all vec4 program compiles (not specific to any
+ * particular program).
+ */
struct {
- struct brw_vs_prog_data *prog_data;
-
- drm_intel_bo *scratch_bo;
- drm_intel_bo *const_bo;
- /** Offset in the program cache to the VS program */
- uint32_t prog_offset;
- uint32_t state_offset;
-
- uint32_t push_const_offset; /* Offset in the batchbuffer */
- int push_const_size; /* in 256-bit register increments */
-
- /** @{ register allocator */
-
struct ra_regs *regs;
/**
* GRF for that object.
*/
uint8_t *ra_reg_to_grf;
- /** @} */
+ } vec4;
- uint32_t bind_bo_offset;
- uint32_t surf_offset[BRW_MAX_VS_SURFACES];
+ struct {
+ struct brw_stage_state base;
+ struct brw_vs_prog_data *prog_data;
} vs;
struct {
+ struct brw_stage_state base;
struct brw_gs_prog_data *prog_data;
+ } gs;
+
+ struct {
+ struct brw_ff_gs_prog_data *prog_data;
bool prog_active;
/** Offset in the program cache to the CLIP program pre-gen6 */
uint32_t state_offset;
uint32_t bind_bo_offset;
- uint32_t surf_offset[BRW_MAX_GS_SURFACES];
- } gs;
+ uint32_t surf_offset[BRW_MAX_GEN6_GS_SURFACES];
+ } ff_gs;
struct {
struct brw_clip_prog_data *prog_data;
} sf;
struct {
+ struct brw_stage_state base;
struct brw_wm_prog_data *prog_data;
- /** offsets in the batch to sampler default colors (texture border color)
- */
- uint32_t sdc_offset[BRW_MAX_TEX_UNIT];
-
GLuint render_surf;
- drm_intel_bo *scratch_bo;
-
/**
* Buffer object used in place of multisampled null render targets on
* Gen6. See brw_update_null_renderbuffer_surface().
*/
drm_intel_bo *multisampled_null_render_target_bo;
- /** Offset in the program cache to the WM program */
- uint32_t prog_offset;
-
- uint32_t state_offset; /* offset in batchbuffer to pre-gen6 WM state */
-
- drm_intel_bo *const_bo; /* pull constant buffer. */
- /**
- * This is offset in the batch to the push constants on gen6.
- *
- * Pre-gen6, push constants live in the CURBE.
- */
- uint32_t push_const_offset;
-
- /** Binding table of pointers to surf_bo entries */
- uint32_t bind_bo_offset;
- uint32_t surf_offset[BRW_MAX_WM_SURFACES];
-
struct {
struct ra_regs *regs;
- /** Array of the ra classes for the unaligned contiguous
- * register block sizes used.
+ /**
+ * Array of the ra classes for the unaligned contiguous register
+ * block sizes used, indexed by register size.
*/
- int *classes;
+ int classes[16];
/**
* Mapping for register-allocated objects in *regs to the first
bool begin_emitted;
} query;
+ struct {
+ /* A map describing which counters are stored at a particular 32-bit
+ * offset in the buffer object.
+ */
+ const struct brw_perf_bo_layout *bo_layout;
+
+ /* Number of 32-bit entries in the buffer object. */
+ int entries_in_bo;
+ } perfmon;
+
int num_atoms;
const struct brw_tracked_state **atoms;
} *state_batch_list;
int state_batch_count;
- struct brw_sol_state {
- uint32_t svbi_0_starting_index;
- uint32_t svbi_0_max_index;
- uint32_t offset_0_batch_start;
- uint32_t primitives_generated;
- uint32_t primitives_written;
- bool counting_primitives_generated;
- bool counting_primitives_written;
- } sol;
-
uint32_t render_target_format[MESA_FORMAT_COUNT];
bool format_supported_as_render_target[MESA_FORMAT_COUNT];
+ /* Interpolation modes, one byte per vue slot.
+ * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
+ */
+ struct interpolation_mode_map interpolation_mode;
+
/* PrimitiveRestart */
struct {
bool in_progress;
int max_entries;
double report_time;
} shader_time;
+
+ __DRIcontext *driContext;
+ struct intel_screen *intelScreen;
+ void (*saved_viewport)(struct gl_context *ctx,
+ GLint x, GLint y, GLsizei width, GLsizei height);
};
/*======================================================================
/*======================================================================
* brw_context.c
*/
-bool brwCreateContext(int api,
+bool brwCreateContext(gl_api api,
const struct gl_config *mesaVis,
__DRIcontext *driContextPriv,
unsigned major_version,
void brw_workaround_depthstencil_alignment(struct brw_context *brw,
GLbitfield clear_mask);
+/* brw_object_purgeable.c */
+void brw_init_object_purgeable_functions(struct dd_function_table *functions);
+
/*======================================================================
* brw_queryobj.c
*/
-void brw_init_queryobj_functions(struct dd_function_table *functions);
+void brw_init_common_queryobj_functions(struct dd_function_table *functions);
+void gen4_init_queryobj_functions(struct dd_function_table *functions);
void brw_emit_query_begin(struct brw_context *brw);
void brw_emit_query_end(struct brw_context *brw);
+/** gen6_queryobj.c */
+void gen6_init_queryobj_functions(struct dd_function_table *functions);
+
/*======================================================================
* brw_state_dump.c
*/
-void brw_debug_batch(struct intel_context *intel);
-void brw_annotate_aub(struct intel_context *intel);
+void brw_debug_batch(struct brw_context *brw);
+void brw_annotate_aub(struct brw_context *brw);
/*======================================================================
* brw_tex.c
void brwInitFragProgFuncs( struct dd_function_table *functions );
int brw_get_scratch_size(int size);
-void brw_get_scratch_bo(struct intel_context *intel,
+void brw_get_scratch_bo(struct brw_context *brw,
drm_intel_bo **scratch_bo, int size);
void brw_init_shader_time(struct brw_context *brw);
int brw_get_shader_time_index(struct brw_context *brw,
*/
void brw_fs_alloc_reg_sets(struct brw_context *brw);
+/* brw_vec4_reg_allocate.cpp */
+void brw_vec4_alloc_reg_set(struct brw_context *brw);
+
/* brw_disasm.c */
int brw_disasm (FILE *file, struct brw_instruction *inst, int gen);
/* brw_vs.c */
gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
+/* brw_draw_upload.c */
+unsigned brw_get_vertex_surface_type(struct brw_context *brw,
+ const struct gl_client_array *glarray);
+unsigned brw_get_index_type(GLenum type);
+
/* brw_wm_surface_state.c */
void brw_init_surface_formats(struct brw_context *brw);
void
struct gl_shader *shader,
uint32_t *surf_offsets);
+/* brw_surface_formats.c */
+bool brw_is_hiz_depth_format(struct brw_context *ctx, gl_format format);
+bool brw_render_target_supported(struct brw_context *brw,
+ struct gl_renderbuffer *rb);
+
+/* brw_performance_monitor.c */
+void brw_init_performance_monitors(struct brw_context *brw);
+
/* gen6_sol.c */
void
brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
/* gen7_sol_state.c */
void
+gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
+ struct gl_transform_feedback_object *obj);
+void
gen7_end_transform_feedback(struct gl_context *ctx,
struct gl_transform_feedback_object *obj);
/* brw_blorp_blit.cpp */
GLbitfield
-brw_blorp_framebuffer(struct intel_context *intel,
+brw_blorp_framebuffer(struct brw_context *brw,
GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
GLbitfield mask, GLenum filter);
bool
-brw_blorp_copytexsubimage(struct intel_context *intel,
+brw_blorp_copytexsubimage(struct brw_context *brw,
struct gl_renderbuffer *src_rb,
struct gl_texture_image *dst_image,
+ int slice,
int srcX0, int srcY0,
int dstX0, int dstY0,
int width, int height);
/* gen7_urb.c */
void
-gen7_allocate_push_constants(struct brw_context *brw);
+gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
+ unsigned gs_size, unsigned fs_size);
void
-gen7_emit_urb_state(struct brw_context *brw, GLuint nr_vs_entries,
- GLuint vs_size, GLuint vs_start);
+gen7_emit_urb_state(struct brw_context *brw,
+ unsigned nr_vs_entries, unsigned vs_size,
+ unsigned vs_start, unsigned nr_gs_entries,
+ unsigned gs_size, unsigned gs_start);
brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
uint32_t prog_offset)
{
- struct intel_context *intel = &brw->intel;
-
- if (intel->gen >= 5) {
+ if (brw->gen >= 5) {
/* Using state base address. */
return prog_offset;
}
- drm_intel_bo_emit_reloc(intel->batch.bo,
+ drm_intel_bo_emit_reloc(brw->batch.bo,
state_offset,
brw->cache.bo,
prog_offset,
}
bool brw_do_cubemap_normalize(struct exec_list *instructions);
-bool brw_lower_texture_gradients(struct intel_context *intel,
+bool brw_lower_texture_gradients(struct brw_context *brw,
struct exec_list *instructions);
struct opcode_desc {
uint32_t width, uint32_t height,
uint32_t tile_x, uint32_t tile_y);
+extern const GLuint prim_to_hw_prim[GL_TRIANGLE_STRIP_ADJACENCY+1];
+
+void
+brw_setup_vec4_key_clip_info(struct brw_context *brw,
+ struct brw_vec4_prog_key *key,
+ bool program_uses_clip_distance);
+
+void
+gen6_upload_vec4_push_constants(struct brw_context *brw,
+ const struct gl_program *prog,
+ const struct brw_vec4_prog_data *prog_data,
+ struct brw_stage_state *stage_state,
+ enum state_struct_type type);
+
#ifdef __cplusplus
}
#endif
projects / mesa.git / blobdiff