struct brw_vec4_prog_key;
struct brw_wm_prog_key;
struct brw_wm_prog_data;
+struct brw_perf_bo_layout;
enum brw_state_id {
BRW_STATE_URB_FENCE,
*/
struct brw_wm_prog_data {
GLuint curb_read_length;
- GLuint urb_read_length;
+ GLuint num_varying_inputs;
GLuint first_curbe_grf;
GLuint first_curbe_grf_16;
*/
uint32_t barycentric_interp_modes;
+ /**
+ * Map from gl_varying_slot to the position within the FS setup data
+ * payload where the varying's attribute vertex deltas should be delivered.
+ * For varying slots that are not used by the FS, the value is -1.
+ */
+ int urb_setup[VARYING_SLOT_MAX];
+
/* Pointers to tracked values (only valid once
* _mesa_load_state_parameters has been called at runtime).
*
}
void brw_compute_vue_map(struct brw_context *brw, struct brw_vue_map *vue_map,
- GLbitfield64 slots_valid, bool userclip_active);
+ GLbitfield64 slots_valid);
+
+
+/**
+ * Bitmask indicating which fragment shader inputs represent varyings (and
+ * hence have to be delivered to the fragment shader by the SF/SBE stage).
+ */
+#define BRW_FS_VARYING_INPUT_MASK \
+ (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
+ ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
/*
GLuint urb_entry_size;
};
+
+/**
+ * We always program SF to start reading at an offset of 1 (2 varying slots)
+ * from the start of the vertex URB entry. This causes it to skip:
+ * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
+ * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
+ */
+#define BRW_SF_URB_ENTRY_READ_OFFSET 1
+
+
struct brw_clip_prog_data {
GLuint curb_read_length; /* user planes? */
GLuint clip_mode;
unsigned output_vertex_size_hwords;
unsigned output_topology;
+
+ /**
+ * Size of the control data (cut bits or StreamID bits), in hwords (32
+ * bytes). 0 if there is no control data.
+ */
+ unsigned control_data_header_size_hwords;
+
+ /**
+ * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
+ * if the control data is StreamID bits, or
+ * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
+ * Ignored if control_data_header_size is 0.
+ */
+ unsigned control_data_format;
+
+ bool include_primitive_id;
};
/** Number of texture sampler units */
* | . | . |
* | : | : |
* | 36 | UBO 11 |
+ * |-----|-------------------------|
+ * | 37 | Shader time buffer |
+ * |-----|-------------------------|
+ * | 38 | Gather texture 0 |
+ * | . | . |
+ * | : | : |
+ * | 53 | Gather texture 15 |
* +-------------------------------+
*
* Our VS (and Gen7 GS) binding tables are programmed as follows:
* | . | . |
* | : | : |
* | 28 | UBO 11 |
+ * |-----|-------------------------|
+ * | 29 | Shader time buffer |
+ * |-----|-------------------------|
+ * | 30 | Gather texture 0 |
+ * | . | . |
+ * | : | : |
+ * | 45 | Gather texture 15 |
* +-------------------------------+
*
* Our (gen6) GS binding tables are programmed as follows:
#define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
#define SURF_INDEX_WM_UBO(u) (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u)
#define SURF_INDEX_WM_SHADER_TIME (SURF_INDEX_WM_UBO(12))
+#define SURF_INDEX_GATHER_TEXTURE(t) (SURF_INDEX_WM_SHADER_TIME + 1 + (t))
/** Maximum size of the binding table. */
-#define BRW_MAX_WM_SURFACES (SURF_INDEX_WM_SHADER_TIME + 1)
+#define BRW_MAX_WM_SURFACES (SURF_INDEX_GATHER_TEXTURE(BRW_MAX_TEX_UNIT))
#define SURF_INDEX_VEC4_CONST_BUFFER (0)
#define SURF_INDEX_VEC4_TEXTURE(t) (SURF_INDEX_VEC4_CONST_BUFFER + 1 + (t))
#define SURF_INDEX_VEC4_UBO(u) (SURF_INDEX_VEC4_TEXTURE(BRW_MAX_TEX_UNIT) + u)
#define SURF_INDEX_VEC4_SHADER_TIME (SURF_INDEX_VEC4_UBO(12))
-#define BRW_MAX_VEC4_SURFACES (SURF_INDEX_VEC4_SHADER_TIME + 1)
+#define SURF_INDEX_VEC4_GATHER_TEXTURE(t) (SURF_INDEX_VEC4_SHADER_TIME + 1 + (t))
+#define BRW_MAX_VEC4_SURFACES (SURF_INDEX_VEC4_GATHER_TEXTURE(BRW_MAX_TEX_UNIT))
#define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
#define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
#define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
#define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
#define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
+#define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
+#define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
#define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
#define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
#define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
struct brw_cached_batch_item *next;
};
-
-
-/* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
- * be easier if C allowed arrays of packed elements?
- */
-#define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
-
struct brw_vertex_buffer {
/** Buffer object containing the uploaded vertex data */
drm_intel_bo *bo;
*/
struct brw_stage_state
{
+ /**
+ * Optional scratch buffer used to store spilled register values and
+ * variably-indexed GRF arrays.
+ */
drm_intel_bo *scratch_bo;
+
+ /** Pull constant buffer */
drm_intel_bo *const_bo;
+
/** Offset in the program cache to the program */
uint32_t prog_offset;
+
+ /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
uint32_t state_offset;
uint32_t push_const_offset; /* Offset in the batchbuffer */
int push_const_size; /* in 256-bit register increments */
+ /* Binding table: pointers to SURFACE_STATE entries. */
uint32_t bind_bo_offset;
- uint32_t surf_offset[BRW_MAX_VEC4_SURFACES];
+ uint32_t surf_offset[BRW_MAX_WM_SURFACES];
/** SAMPLER_STATE count and table offset */
uint32_t sampler_count;
void (*update_texture_surface)(struct gl_context *ctx,
unsigned unit,
- uint32_t *binding_table,
- unsigned surf_index);
+ uint32_t *surf_offset,
+ bool for_gather);
void (*update_renderbuffer_surface)(struct brw_context *brw,
struct gl_renderbuffer *rb,
bool layered,
bool always_flush_cache;
bool disable_throttling;
bool precompile;
+ bool disable_derivative_optimization;
driOptionCache optionCache;
/** @} */
bool constrained;
+ GLuint min_vs_entries; /* Minimum number of VS entries */
GLuint max_vs_entries; /* Maximum number of VS entries */
GLuint max_gs_entries; /* Maximum number of GS entries */
} sf;
struct {
+ struct brw_stage_state base;
struct brw_wm_prog_data *prog_data;
GLuint render_surf;
- drm_intel_bo *scratch_bo;
-
/**
* Buffer object used in place of multisampled null render targets on
* Gen6. See brw_update_null_renderbuffer_surface().
*/
drm_intel_bo *multisampled_null_render_target_bo;
- /** Offset in the program cache to the WM program */
- uint32_t prog_offset;
-
- uint32_t state_offset; /* offset in batchbuffer to pre-gen6 WM state */
-
- drm_intel_bo *const_bo; /* pull constant buffer. */
- /**
- * This is offset in the batch to the push constants on gen6.
- *
- * Pre-gen6, push constants live in the CURBE.
- */
- uint32_t push_const_offset;
-
- /** Binding table of pointers to surf_bo entries */
- uint32_t bind_bo_offset;
- uint32_t surf_offset[BRW_MAX_WM_SURFACES];
-
- /** SAMPLER_STATE count and table offset */
- uint32_t sampler_count;
- uint32_t sampler_offset;
-
- /** Offsets in the batch to sampler default colors (texture border color)
- */
- uint32_t sdc_offset[BRW_MAX_TEX_UNIT];
-
struct {
struct ra_regs *regs;
- /** Array of the ra classes for the unaligned contiguous
- * register block sizes used.
+ /**
+ * Array of the ra classes for the unaligned contiguous register
+ * block sizes used, indexed by register size.
*/
- int *classes;
+ int classes[16];
/**
* Mapping for register-allocated objects in *regs to the first
bool begin_emitted;
} query;
+ struct {
+ /* A map describing which counters are stored at a particular 32-bit
+ * offset in the buffer object.
+ */
+ const struct brw_perf_bo_layout *bo_layout;
+
+ /* Number of 32-bit entries in the buffer object. */
+ int entries_in_bo;
+ } perfmon;
+
int num_atoms;
const struct brw_tracked_state **atoms;
/*======================================================================
* brw_context.c
*/
-bool brwCreateContext(int api,
+bool brwCreateContext(gl_api api,
const struct gl_config *mesaVis,
__DRIcontext *driContextPriv,
unsigned major_version,
bool brw_render_target_supported(struct brw_context *brw,
struct gl_renderbuffer *rb);
+/* brw_performance_monitor.c */
+void brw_init_performance_monitors(struct brw_context *brw);
+
/* gen6_sol.c */
void
brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
uint32_t width, uint32_t height,
uint32_t tile_x, uint32_t tile_y);
-extern const GLuint prim_to_hw_prim[GL_POLYGON+1];
+extern const GLuint prim_to_hw_prim[GL_TRIANGLE_STRIP_ADJACENCY+1];
void
brw_setup_vec4_key_clip_info(struct brw_context *brw,
struct brw_vec4_prog_key *key,
bool program_uses_clip_distance);
+void
+gen6_upload_vec4_push_constants(struct brw_context *brw,
+ const struct gl_program *prog,
+ const struct brw_vec4_prog_data *prog_data,
+ struct brw_stage_state *stage_state,
+ enum state_struct_type type);
+
#ifdef __cplusplus
}
#endif
projects / mesa.git / blobdiff