i965: Add new SIMD8 VS prog data flag

[mesa.git] / src / mesa / drivers / dri / i965 / brw_context.h

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index e678bde4599932c462d1315d884193fa9ae3f5f5..7a6ec2fda944a65e40048b261c8a8ddc366b04a3 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -201,6 +201,7 @@ enum brw_state_id {
    BRW_STATE_SF_VP,
    BRW_STATE_CLIP_VP,
    BRW_STATE_SAMPLER_STATE_TABLE,
+   BRW_STATE_VS_ATTRIB_WORKAROUNDS,
    BRW_NUM_STATE_BITS
 };
 
@@ -279,6 +280,7 @@ enum brw_state_id {
 #define BRW_NEW_SF_VP                   (1ull << BRW_STATE_SF_VP)
 #define BRW_NEW_CLIP_VP                 (1ull << BRW_STATE_CLIP_VP)
 #define BRW_NEW_SAMPLER_STATE_TABLE     (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
+#define BRW_NEW_VS_ATTRIB_WORKAROUNDS   (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
 
 struct brw_state_flags {
    /** State update flags signalled by mesa internals */
@@ -287,15 +289,6 @@ struct brw_state_flags {
     * State update flags signalled as the result of brw_tracked_state updates
     */
    uint64_t brw;
-   /**
-    * State update flags that used to be signalled by brw_state_cache.c
-    * searches.
-    *
-    * Now almost all of that state is just streamed out on demand, but the
-    * flags for those state blobs updating have stayed in the same bitfield.
-    * brw_state_cache.c still flags BRW_NEW_*_PROG_DATA.
-    */
-   GLuint cache;
 };
 
 /** Subclass of Mesa vertex program */
@@ -364,6 +357,8 @@ struct brw_stage_prog_data {
     */
    unsigned dispatch_grf_start_reg;
 
+   bool use_alt_mode; /**< Use ALT floating point mode?  Otherwise, IEEE. */
+
    /* Pointers to tracked values (only valid once
     * _mesa_load_state_parameters has been called at runtime).
     *
@@ -399,6 +394,8 @@ struct brw_wm_prog_data {
       /** @} */
    } binding_table;
 
+   uint8_t computed_depth_mode;
+
    bool no_8;
    bool dual_src_blend;
    bool uses_pos_offset;
@@ -598,6 +595,8 @@ struct brw_vec4_prog_data {
     * is the size of the URB entry used for output.
     */
    GLuint urb_entry_size;
+
+   bool simd8;
 };
 
 
@@ -740,8 +739,7 @@ struct brw_gs_prog_data
 struct brw_cache_item {
    /**
     * Effectively part of the key, cache_id identifies what kind of state
-    * buffer is involved, and also which brw->state.dirty.cache flag should
-    * be set when this cache item is chosen.
+    * buffer is involved, and also which dirty flag should set.
     */
    enum brw_cache_id cache_id;
    /** 32-bit hash of the key data */
@@ -1139,6 +1137,14 @@ struct brw_context
        * the same VB packed over and over again.
        */
       unsigned int start_vertex_bias;
+
+      /**
+       * Certain vertex attribute formats aren't natively handled by the
+       * hardware and require special VS code to fix up their values.
+       *
+       * These bitfields indicate which workarounds are needed.
+       */
+      uint8_t attrib_wa_flags[VERT_ATTRIB_MAX];
    } vb;
 
    struct {
@@ -1614,7 +1620,8 @@ brw_update_sol_surface(struct brw_context *brw,
 void brw_upload_ubo_surfaces(struct brw_context *brw,
                             struct gl_shader *shader,
                              struct brw_stage_state *stage_state,
-                             struct brw_stage_prog_data *prog_data);
+                             struct brw_stage_prog_data *prog_data,
+                             bool dword_pitch);
 void brw_upload_abo_surfaces(struct brw_context *brw,
                              struct gl_shader_program *prog,
                              struct brw_stage_state *stage_state,