i965: Start adding the VS visitor and codegen.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_context.h

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index a8e2b80280315931dc9b970a5b83d69d26d70132..7b6b64c1a5c384eafac9872e6b1e8782d2227a0a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -188,6 +188,32 @@ struct brw_state_flags {
    GLuint cache;
 };
 
+enum state_struct_type {
+   AUB_TRACE_VS_STATE =                        1,
+   AUB_TRACE_GS_STATE =                        2,
+   AUB_TRACE_CLIP_STATE =              3,
+   AUB_TRACE_SF_STATE =                        4,
+   AUB_TRACE_WM_STATE =                        5,
+   AUB_TRACE_CC_STATE =                        6,
+   AUB_TRACE_CLIP_VP_STATE =           7,
+   AUB_TRACE_SF_VP_STATE =             8,
+   AUB_TRACE_CC_VP_STATE =             0x9,
+   AUB_TRACE_SAMPLER_STATE =           0xa,
+   AUB_TRACE_KERNEL_INSTRUCTIONS =     0xb,
+   AUB_TRACE_SCRATCH_SPACE =           0xc,
+   AUB_TRACE_SAMPLER_DEFAULT_COLOR =    0xd,
+
+   AUB_TRACE_SCISSOR_STATE =           0x15,
+   AUB_TRACE_BLEND_STATE =             0x16,
+   AUB_TRACE_DEPTH_STENCIL_STATE =     0x17,
+
+   /* Not written to .aub files the same way the structures above are. */
+   AUB_TRACE_NO_TYPE =                 0x100,
+   AUB_TRACE_BINDING_TABLE =           0x101,
+   AUB_TRACE_SURFACE_STATE =           0x102,
+   AUB_TRACE_VS_CONSTANTS =            0x103,
+   AUB_TRACE_WM_CONSTANTS =            0x104,
+};
 
 /** Subclass of Mesa vertex program */
 struct brw_vertex_program {
@@ -503,7 +529,7 @@ struct brw_context
        * the CURBE, the depth buffer, and a query BO.
        */
       drm_intel_bo *validated_bos[VERT_ATTRIB_MAX + BRW_WM_MAX_SURF + 16];
-      int validated_bo_count;
+      unsigned int validated_bo_count;
    } state;
 
    struct brw_cache cache;
@@ -722,6 +748,29 @@ struct brw_context
        * Pre-gen6, push constants live in the CURBE.
        */
       uint32_t push_const_offset;
+
+      /** @{ register allocator */
+
+      struct ra_regs *regs;
+
+      /** Array of the ra classes for the unaligned contiguous
+       * register block sizes used.
+       */
+      int *classes;
+
+      /**
+       * Mapping for register-allocated objects in *regs to the first
+       * GRF for that object.
+      */
+      uint8_t *ra_reg_to_grf;
+
+      /**
+       * ra class for the aligned pairs we use for PLN, which doesn't
+       * appear in *classes.
+       */
+      int aligned_pairs_class;
+
+      /** @} */
    } wm;
 
 
@@ -744,6 +793,14 @@ struct brw_context
 
    int num_prepare_atoms, num_emit_atoms;
    struct brw_tracked_state prepare_atoms[64], emit_atoms[64];
+
+   /* If (INTEL_DEBUG & DEBUG_BATCH) */
+   struct {
+      uint32_t offset;
+      uint32_t size;
+      enum state_struct_type type;
+   } *state_batch_list;
+   int state_batch_count;
 };