#include "isl/isl.h"
#include "blorp/blorp.h"
-#ifdef __cplusplus
-extern "C" {
- /* Evil hack for using libdrm in a c++ compiler. */
- #define virtual virt
-#endif
-
#include <intel_bufmgr.h>
-#ifdef __cplusplus
- #undef virtual
-}
-#endif
-#ifdef __cplusplus
-extern "C" {
-#endif
#include "intel_debug.h"
#include "intel_screen.h"
#include "intel_tex_obj.h"
#include "intel_resolve_map.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
/* Glossary:
*
* URB - uniform resource buffer. A mid-sized buffer which is
};
-struct gen4_fragment_program {
- struct brw_program base;
-
- bool contains_flat_varying;
- bool contains_noperspective_varying;
-
- /*
- * Mapping of varying slots to interpolation modes.
- * Used Gen4/5 by the clip|sf|wm stages.
- */
- unsigned char interp_mode[BRW_VARYING_SLOT_COUNT];
-};
-
-
-/**
- * Bitmask indicating which fragment shader inputs represent varyings (and
- * hence have to be delivered to the fragment shader by the SF/SBE stage).
- */
-#define BRW_FS_VARYING_INPUT_MASK \
- (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
- ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
-
-
struct brw_sf_prog_data {
GLuint urb_read_length;
GLuint total_grf;
};
-/**
- * We always program SF to start reading at an offset of 1 (2 varying slots)
- * from the start of the vertex URB entry. This causes it to skip:
- * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
- * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
- */
-#define BRW_SF_URB_ENTRY_READ_OFFSET 1
-
-
struct brw_clip_prog_data {
GLuint curb_read_length; /* user planes? */
GLuint clip_mode;
*/
#define SHADER_TIME_STRIDE 64
-struct brw_cache_item {
- /**
- * Effectively part of the key, cache_id identifies what kind of state
- * buffer is involved, and also which dirty flag should set.
- */
- enum brw_cache_id cache_id;
- /** 32-bit hash of the key data */
- GLuint hash;
- GLuint key_size; /* for variable-sized keys */
- GLuint aux_size;
- const void *key;
-
- uint32_t offset;
- uint32_t size;
-
- struct brw_cache_item *next;
-};
-
-
struct brw_cache {
struct brw_context *brw;
} saved;
};
-#define MAX_GS_INPUT_VERTICES 6
-
#define BRW_MAX_XFB_STREAMS 4
struct brw_transform_feedback_object {
/** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
GLenum primitive_mode;
+ /**
+ * The maximum number of vertices that we can write without overflowing
+ * any of the buffers currently being used for transform feedback.
+ */
+ unsigned max_index;
+
/**
* Count of primitives generated during this transform feedback operation.
* @{
struct gen_l3_config;
+enum brw_query_kind {
+ PIPELINE_STATS
+};
+
+struct brw_perf_query_info
+{
+ enum brw_query_kind kind;
+ const char *name;
+ struct brw_perf_query_counter *counters;
+ int n_counters;
+ size_t data_size;
+};
+
/**
* brw_context is derived from gl_context.
*/
bool supported;
} predicate;
+ struct {
+ struct brw_perf_query_info *queries;
+ int n_queries;
+
+ int n_active_pipeline_stats_queries;
+ } perfquery;
+
int num_atoms[BRW_NUM_PIPELINES];
const struct brw_tracked_state render_atoms[76];
const struct brw_tracked_state compute_atoms[11];
/*======================================================================
* brw_misc_state.c
*/
-void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
- uint32_t depth_level,
- uint32_t depth_layer,
- struct intel_mipmap_tree *stencil_mt,
- uint32_t *out_tile_mask_x,
- uint32_t *out_tile_mask_y);
void brw_workaround_depthstencil_alignment(struct brw_context *brw,
GLbitfield clear_mask);
void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *bo, int idx);
/** hsw_queryobj.c */
+void hsw_overflow_result_to_gpr0(struct brw_context *brw,
+ struct brw_query_object *query,
+ int count);
void hsw_init_queryobj_functions(struct dd_function_table *functions);
/** brw_conditional_render.c */
void brwInitFragProgFuncs( struct dd_function_table *functions );
-/* Per-thread scratch space is a power-of-two multiple of 1KB. */
-static inline int
-brw_get_scratch_size(int size)
-{
- return MAX2(1024, util_next_power_of_two(size));
-}
void brw_get_scratch_bo(struct brw_context *brw,
drm_intel_bo **scratch_bo, int size);
void brw_alloc_stage_scratch(struct brw_context *brw,
*/
void brw_upload_cs_urb_state(struct brw_context *brw);
-/* brw_fs_reg_allocate.cpp
- */
-void brw_fs_alloc_reg_sets(struct brw_compiler *compiler);
-
-/* brw_vec4_reg_allocate.cpp */
-void brw_vec4_alloc_reg_set(struct brw_compiler *compiler);
-
-/* brw_disasm.c */
-int brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
- struct brw_inst *inst, bool is_compacted);
-
/* brw_vs.c */
gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
struct gl_renderbuffer *rb);
uint32_t brw_depth_format(struct brw_context *brw, mesa_format format);
+/* brw_performance_query.c */
+void brw_init_performance_queries(struct brw_context *brw);
+
/* intel_buffer_objects.c */
int brw_bo_map(struct brw_context *brw, drm_intel_bo *bo, int write_enable,
const char *bo_name);
void
brw_end_transform_feedback(struct gl_context *ctx,
struct gl_transform_feedback_object *obj);
+void
+brw_pause_transform_feedback(struct gl_context *ctx,
+ struct gl_transform_feedback_object *obj);
+void
+brw_resume_transform_feedback(struct gl_context *ctx,
+ struct gl_transform_feedback_object *obj);
+void
+brw_save_primitives_written_counters(struct brw_context *brw,
+ struct brw_transform_feedback_object *obj);
+void
+brw_compute_xfb_vertices_written(struct brw_context *brw,
+ struct brw_transform_feedback_object *obj);
GLsizei
brw_get_transform_feedback_vertex_count(struct gl_context *ctx,
struct gl_transform_feedback_object *obj,
bool brw_do_cubemap_normalize(struct exec_list *instructions);
-extern const char * const conditional_modifier[16];
-extern const char *const pred_ctrl_align16[16];
-
static inline bool
brw_depth_writes_enabled(const struct brw_context *brw)
{
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