i965: Pass brw rather than gen to brw_disassemble_inst().
[mesa.git] / src / mesa / drivers / dri / i965 / brw_context.h
index 80dba1011fa70a22e4a24fd0cdbf311e646d980f..c3c82297d4e376583d686800871bfcd744f639d8 100644 (file)
@@ -181,6 +181,7 @@ enum brw_state_id {
    BRW_STATE_META_IN_PROGRESS,
    BRW_STATE_INTERPOLATION_MAP,
    BRW_STATE_PUSH_CONSTANT_ALLOCATION,
+   BRW_STATE_NUM_SAMPLES,
    BRW_NUM_STATE_BITS
 };
 
@@ -220,6 +221,7 @@ enum brw_state_id {
 #define BRW_NEW_META_IN_PROGRESS        (1 << BRW_STATE_META_IN_PROGRESS)
 #define BRW_NEW_INTERPOLATION_MAP       (1 << BRW_STATE_INTERPOLATION_MAP)
 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
+#define BRW_NEW_NUM_SAMPLES             (1 << BRW_STATE_NUM_SAMPLES)
 
 struct brw_state_flags {
    /** State update flags signalled by mesa internals */
@@ -820,12 +822,6 @@ enum shader_time_shader_type {
 #define CACHE_NEW_CLIP_UNIT              (1<<BRW_CLIP_UNIT)
 #define CACHE_NEW_CLIP_PROG              (1<<BRW_CLIP_PROG)
 
-struct brw_cached_batch_item {
-   struct header *header;
-   GLuint sz;
-   struct brw_cached_batch_item *next;
-};
-
 struct brw_vertex_buffer {
    /** Buffer object containing the uploaded vertex data */
    drm_intel_bo *bo;
@@ -839,8 +835,6 @@ struct brw_vertex_element {
 
    int buffer;
 
-   /** The corresponding Mesa vertex attribute */
-   gl_vert_attrib attrib;
    /** Offset of the first element within the buffer object */
    unsigned int offset;
 };
@@ -877,8 +871,6 @@ struct intel_batchbuffer {
    drm_intel_bo *workaround_bo;
    bool need_workaround_flush;
 
-   struct cached_batch_item *cached_items;
-
    uint16_t emit, total;
    uint16_t used, reserved_space;
    uint32_t *map;
@@ -933,6 +925,7 @@ struct brw_transform_feedback_object {
  */
 struct brw_stage_state
 {
+   gl_shader_stage stage;
    struct brw_stage_prog_data *prog_data;
 
    /**
@@ -941,9 +934,6 @@ struct brw_stage_state
     */
    drm_intel_bo *scratch_bo;
 
-   /** Pull constant buffer */
-   drm_intel_bo *const_bo;
-
    /** Offset in the program cache to the program */
    uint32_t prog_offset;
 
@@ -1005,9 +995,7 @@ struct brw_context
       /** Upload a SAMPLER_STATE table. */
       void (*upload_sampler_state_table)(struct brw_context *brw,
                                          struct gl_program *prog,
-                                         uint32_t sampler_count,
-                                         uint32_t *sst_offset,
-                                         uint32_t *sdc_offset);
+                                         struct brw_stage_state *stage_state);
 
       /**
        * Send the appropriate state packets to configure depth, stencil, and
@@ -1049,10 +1037,7 @@ struct brw_context
 
    struct {
       drm_intel_bo *bo;
-      GLuint offset;
-      uint32_t buffer_len;
-      uint32_t buffer_offset;
-      char buffer[4096];
+      uint32_t next_offset;
    } upload;
 
    /**
@@ -1129,11 +1114,16 @@ struct brw_context
    } state;
 
    struct brw_cache cache;
-   struct brw_cached_batch_item *cached_batch_items;
+
+   /** IDs for meta stencil blit shader programs. */
+   unsigned meta_stencil_blit_programs[2];
 
    /* Whether a meta-operation is in progress. */
    bool meta_in_progress;
 
+   /* Whether the last depth/stencil packets were both NULL. */
+   bool no_depth_or_stencil;
+
    struct {
       struct brw_vertex_element inputs[VERT_ATTRIB_MAX];
       struct brw_vertex_buffer buffers[VERT_ATTRIB_MAX];
@@ -1178,10 +1168,11 @@ struct brw_context
    const struct gl_geometry_program *geometry_program;
    const struct gl_fragment_program *fragment_program;
 
-   /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
-   uint32_t CMD_VF_STATISTICS;
-   /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
-   uint32_t CMD_PIPELINE_SELECT;
+   /**
+    * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
+    * that we don't have to reemit that state every time we change FBOs.
+    */
+   int num_samples;
 
    /**
     * Platform specific constants containing the maximum number of threads
@@ -1445,12 +1436,6 @@ struct brw_context
    struct intel_screen *intelScreen;
 };
 
-static inline bool
-is_power_of_two(uint32_t value)
-{
-   return (value & (value - 1)) == 0;
-}
-
 /*======================================================================
  * brw_vtbl.c
  */
@@ -1490,6 +1475,26 @@ GLboolean brwCreateContext(gl_api api,
                       unsigned *error,
                      void *sharedContextPrivate);
 
+/*======================================================================
+ * brw_misc_state.c
+ */
+GLuint brw_get_rb_for_slice(struct brw_context *brw,
+                            struct intel_mipmap_tree *mt,
+                            unsigned level, unsigned layer, bool flat);
+
+void brw_meta_updownsample(struct brw_context *brw,
+                           struct intel_mipmap_tree *src,
+                           struct intel_mipmap_tree *dst);
+
+void brw_meta_fbo_stencil_blit(struct brw_context *brw,
+                               GLfloat srcX0, GLfloat srcY0,
+                               GLfloat srcX1, GLfloat srcY1,
+                               GLfloat dstX0, GLfloat dstY0,
+                               GLfloat dstX1, GLfloat dstY1);
+
+void brw_meta_stencil_updownsample(struct brw_context *brw,
+                                   struct intel_mipmap_tree *src,
+                                   struct intel_mipmap_tree *dst);
 /*======================================================================
  * brw_misc_state.c
  */
@@ -1571,7 +1576,8 @@ void brw_fs_alloc_reg_sets(struct intel_screen *screen);
 void brw_vec4_alloc_reg_set(struct intel_screen *screen);
 
 /* brw_disasm.c */
-int brw_disasm (FILE *file, struct brw_instruction *inst, int gen);
+int brw_disassemble_inst(FILE *file, struct brw_context *brw,
+                         struct brw_instruction *inst, bool is_compacted);
 
 /* brw_vs.c */
 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);