struct brw_context;
struct brw_inst;
struct brw_vs_prog_key;
-struct brw_vec4_prog_key;
+struct brw_vue_prog_key;
struct brw_wm_prog_key;
struct brw_wm_prog_data;
+struct brw_cs_prog_key;
+struct brw_cs_prog_data;
+
+enum brw_pipeline {
+ BRW_RENDER_PIPELINE,
+ BRW_COMPUTE_PIPELINE,
+
+ BRW_NUM_PIPELINES
+};
enum brw_cache_id {
BRW_CACHE_FS_PROG,
BRW_CACHE_FF_GS_PROG,
BRW_CACHE_GS_PROG,
BRW_CACHE_CLIP_PROG,
+ BRW_CACHE_CS_PROG,
BRW_MAX_CACHE
};
BRW_STATE_SF_VP,
BRW_STATE_CLIP_VP,
BRW_STATE_SAMPLER_STATE_TABLE,
+ BRW_STATE_VS_ATTRIB_WORKAROUNDS,
+ BRW_STATE_COMPUTE_PROGRAM,
BRW_NUM_STATE_BITS
};
#define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
#define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
#define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
+#define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
#define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
#define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
#define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
#define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
#define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
#define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
+#define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
+#define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
struct brw_state_flags {
/** State update flags signalled by mesa internals */
* State update flags signalled as the result of brw_tracked_state updates
*/
uint64_t brw;
- /**
- * State update flags that used to be signalled by brw_state_cache.c
- * searches.
- *
- * Now almost all of that state is just streamed out on demand, but the
- * flags for those state blobs updating have stayed in the same bitfield.
- * brw_state_cache.c still flags BRW_NEW_*_PROG_DATA.
- */
- GLuint cache;
};
/** Subclass of Mesa vertex program */
uint32_t gather_texture_start;
uint32_t ubo_start;
uint32_t abo_start;
+ uint32_t image_start;
uint32_t shader_time_start;
/** @} */
} binding_table;
*/
unsigned dispatch_grf_start_reg;
+ bool use_alt_mode; /**< Use ALT floating point mode? Otherwise, IEEE. */
+
/* Pointers to tracked values (only valid once
* _mesa_load_state_parameters has been called at runtime).
*
/** @} */
} binding_table;
+ uint8_t computed_depth_mode;
+
bool no_8;
bool dual_src_blend;
bool uses_pos_offset;
bool uses_omask;
bool uses_kill;
+ bool pulls_bary;
uint32_t prog_offset_16;
/**
int urb_setup[VARYING_SLOT_MAX];
};
+/* Note: brw_cs_prog_data_compare() must be updated when adding fields to this
+ * struct!
+ */
+struct brw_cs_prog_data {
+ struct brw_stage_prog_data base;
+
+ GLuint dispatch_grf_start_reg_16;
+ unsigned local_size[3];
+ unsigned simd_size;
+};
+
/**
* Enum representing the i965-specific vertex results that don't correspond
* exactly to any element of gl_varying_slot. The values of this enum are
return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
}
-void brw_compute_vue_map(struct brw_context *brw, struct brw_vue_map *vue_map,
+void brw_compute_vue_map(const struct brw_device_info *devinfo,
+ struct brw_vue_map *vue_map,
GLbitfield64 slots_valid);
unsigned svbi_postincrement_value;
};
+enum shader_dispatch_mode {
+ DISPATCH_MODE_4X1_SINGLE = 0,
+ DISPATCH_MODE_4X2_DUAL_INSTANCE = 1,
+ DISPATCH_MODE_4X2_DUAL_OBJECT = 2,
+ DISPATCH_MODE_SIMD8 = 3,
+};
-/* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
+/* Note: brw_vue_prog_data_compare() must be updated when adding fields to
* this struct!
*/
-struct brw_vec4_prog_data {
+struct brw_vue_prog_data {
struct brw_stage_prog_data base;
struct brw_vue_map vue_map;
* is the size of the URB entry used for output.
*/
GLuint urb_entry_size;
+
+ enum shader_dispatch_mode dispatch_mode;
};
* struct!
*/
struct brw_vs_prog_data {
- struct brw_vec4_prog_data base;
+ struct brw_vue_prog_data base;
GLbitfield64 inputs_read;
/** Max number of atomic counter buffer objects in a shader */
#define BRW_MAX_ABO 16
+/** Max number of image uniforms in a shader */
+#define BRW_MAX_IMAGES 32
+
/**
* Max number of binding table entries used for stream output.
*
BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
12 + /* ubo */ \
BRW_MAX_ABO + \
+ BRW_MAX_IMAGES + \
2 /* shader time, pull constants */)
#define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
*/
struct brw_gs_prog_data
{
- struct brw_vec4_prog_data base;
+ struct brw_vue_prog_data base;
/**
* Size of an output vertex, measured in HWORDS (32 bytes).
int invocations;
- /**
- * Dispatch mode, can be any of:
- * GEN7_GS_DISPATCH_MODE_DUAL_OBJECT
- * GEN7_GS_DISPATCH_MODE_DUAL_INSTANCE
- * GEN7_GS_DISPATCH_MODE_SINGLE
- */
- int dispatch_mode;
-
/**
* Gen6 transform feedback enabled flag.
*/
struct brw_cache_item {
/**
* Effectively part of the key, cache_id identifies what kind of state
- * buffer is involved, and also which brw->state.dirty.cache flag should
- * be set when this cache item is chosen.
+ * buffer is involved, and also which dirty flag should set.
*/
enum brw_cache_id cache_id;
/** 32-bit hash of the key data */
enum shader_time_shader_type {
ST_NONE,
ST_VS,
- ST_VS_WRITTEN,
- ST_VS_RESET,
ST_GS,
- ST_GS_WRITTEN,
- ST_GS_RESET,
ST_FS8,
- ST_FS8_WRITTEN,
- ST_FS8_RESET,
ST_FS16,
- ST_FS16_WRITTEN,
- ST_FS16_RESET,
+ ST_CS,
};
struct brw_vertex_buffer {
/** Last index in bo with query data for this object. */
int last_index;
-};
-
-struct intel_sync_object {
- struct gl_sync_object Base;
- /** Batch associated with this sync object */
- drm_intel_bo *bo;
+ /** True if we know the batch has been flushed since we ended the query. */
+ bool flushed;
};
enum brw_gpu_ring {
drm_intel_bo *bo;
/** Last BO submitted to the hardware. Used for glFinish(). */
drm_intel_bo *last_bo;
- /** BO for post-sync nonzero writes for gen6 workaround. */
- drm_intel_bo *workaround_bo;
- bool need_workaround_flush;
+#ifdef DEBUG
uint16_t emit, total;
- uint16_t used, reserved_space;
+#endif
+ uint16_t reserved_space;
+ uint32_t *map_next;
uint32_t *map;
uint32_t *cpu_map;
#define BATCH_SZ (8192*sizeof(uint32_t))
bool needs_sol_reset;
struct {
- uint16_t used;
+ uint32_t *map_next;
int reloc_count;
} saved;
};
uint32_t sampler_offset;
};
+enum brw_predicate_state {
+ /* The first two states are used if we can determine whether to draw
+ * without having to look at the values in the query object buffer. This
+ * will happen if there is no conditional render in progress, if the query
+ * object is already completed or if something else has already added
+ * samples to the preliminary result such as via a BLT command.
+ */
+ BRW_PREDICATE_STATE_RENDER,
+ BRW_PREDICATE_STATE_DONT_RENDER,
+ /* In this case whether to draw or not depends on the result of an
+ * MI_PREDICATE command so the predicate enable bit needs to be checked.
+ */
+ BRW_PREDICATE_STATE_USE_BIT
+};
+
+struct shader_times;
/**
* brw_context is derived from gl_context.
unsigned unit,
uint32_t *surf_offset,
bool for_gather);
- void (*update_renderbuffer_surface)(struct brw_context *brw,
- struct gl_renderbuffer *rb,
- bool layered,
- unsigned unit);
- void (*update_null_renderbuffer_surface)(struct brw_context *brw,
- unsigned unit);
-
- void (*create_raw_surface)(struct brw_context *brw,
- drm_intel_bo *bo,
- uint32_t offset,
- uint32_t size,
- uint32_t *out_offset,
- bool rw);
+ uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
+ struct gl_renderbuffer *rb,
+ bool layered, unsigned unit,
+ uint32_t surf_index);
+
+ void (*emit_texture_surface_state)(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ GLenum target,
+ unsigned min_layer,
+ unsigned max_layer,
+ unsigned min_level,
+ unsigned max_level,
+ unsigned format,
+ unsigned swizzle,
+ uint32_t *surf_offset,
+ bool rw, bool for_gather);
void (*emit_buffer_surface_state)(struct brw_context *brw,
uint32_t *out_offset,
drm_intel_bo *bo,
unsigned surface_format,
unsigned buffer_size,
unsigned pitch,
- unsigned mocs,
bool rw);
+ void (*emit_null_surface_state)(struct brw_context *brw,
+ unsigned width,
+ unsigned height,
+ unsigned samples,
+ uint32_t *out_offset);
/**
* Send the appropriate state packets to configure depth, stencil, and
drm_intel_context *hw_ctx;
+ /** BO for post-sync nonzero writes for gen6 workaround. */
+ drm_intel_bo *workaround_bo;
+ uint8_t pipe_controls_since_last_cs_stall;
+
/**
* Set of drm_intel_bo * that have been rendered to within this batchbuffer
* and would need flushing before being used from another cache domain that
* Number of resets observed in the system at context creation.
*
* This is tracked in the context so that we can determine that another
- * reset has occured.
+ * reset has occurred.
*/
uint32_t reset_count;
} upload;
/**
- * Set if rendering has occured to the drawable's front buffer.
+ * Set if rendering has occurred to the drawable's front buffer.
*
* This is used in the DRI2 case to detect that glFlush should also copy
* the contents of the fake front buffer to the real front buffer.
bool front_buffer_dirty;
/** Framerate throttling: @{ */
- drm_intel_bo *first_post_swapbuffers_batch;
- bool need_throttle;
+ drm_intel_bo *throttle_batch[2];
+
+ /* Limit the number of outstanding SwapBuffers by waiting for an earlier
+ * frame of rendering to complete. This gives a very precise cap to the
+ * latency between input and output such that rendering never gets more
+ * than a frame behind the user. (With the caveat that we technically are
+ * not using the SwapBuffers itself as a barrier but the first batch
+ * submitted afterwards, which may be immediately prior to the next
+ * SwapBuffers.)
+ */
+ bool need_swap_throttle;
+
+ /** General throttling, not caught by throttling between SwapBuffers */
+ bool need_flush_throttle;
/** @} */
GLuint stats_wm;
bool is_baytrail;
bool is_haswell;
bool is_cherryview;
+ bool is_broxton;
bool has_hiz;
bool has_separate_stencil;
bool has_pln;
bool no_simd8;
bool use_rep_send;
+ bool use_resource_streamer;
/**
* Some versions of Gen hardware don't do centroid interpolation correctly
GLuint NewGLState;
struct {
- struct brw_state_flags dirty;
+ struct brw_state_flags pipelines[BRW_NUM_PIPELINES];
} state;
+ enum brw_pipeline last_pipeline;
+
struct brw_cache cache;
/** IDs for meta stencil blit shader programs. */
uint32_t pma_stall_bits;
struct {
- /** Does the current draw use the index buffer? */
- bool indexed;
-
- int start_vertex_location;
- int base_vertex_location;
+ /** The value of gl_BaseVertex for the current _mesa_prim. */
+ int gl_basevertex;
/**
* Buffer and offset used for GL_ARB_shader_draw_parameters
* the same VB packed over and over again.
*/
unsigned int start_vertex_bias;
+
+ /**
+ * Certain vertex attribute formats aren't natively handled by the
+ * hardware and require special VS code to fix up their values.
+ *
+ * These bitfields indicate which workarounds are needed.
+ */
+ uint8_t attrib_wa_flags[VERT_ATTRIB_MAX];
} vb;
struct {
const struct gl_vertex_program *vertex_program;
const struct gl_geometry_program *geometry_program;
const struct gl_fragment_program *fragment_program;
+ const struct gl_compute_program *compute_program;
/**
* Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
* Platform specific constants containing the maximum number of threads
* for each pipeline stage.
*/
- int max_vs_threads;
- int max_gs_threads;
- int max_wm_threads;
+ unsigned max_vs_threads;
+ unsigned max_hs_threads;
+ unsigned max_ds_threads;
+ unsigned max_gs_threads;
+ unsigned max_wm_threads;
+ unsigned max_cs_threads;
/* BRW_NEW_URB_ALLOCATIONS:
*/
GLuint min_vs_entries; /* Minimum number of VS entries */
GLuint max_vs_entries; /* Maximum number of VS entries */
+ GLuint max_hs_entries; /* Maximum number of HS entries */
+ GLuint max_ds_entries; /* Maximum number of DS entries */
GLuint max_gs_entries; /* Maximum number of GS entries */
GLuint nr_vs_entries;
/**
* Buffer object used in place of multisampled null render targets on
- * Gen6. See brw_update_null_renderbuffer_surface().
+ * Gen6. See brw_emit_null_surface_state().
*/
drm_intel_bo *multisampled_null_render_target_bo;
uint32_t fast_clear_op;
} wm;
+ struct {
+ struct brw_stage_state base;
+ struct brw_cs_prog_data *prog_data;
+ } cs;
+
+ /* RS hardware binding table */
+ struct {
+ drm_intel_bo *bo;
+ uint32_t next_offset;
+ } hw_bt_pool;
struct {
uint32_t state_offset;
bool begin_emitted;
} query;
+ struct {
+ enum brw_predicate_state state;
+ bool supported;
+ } predicate;
+
struct {
/** A map from pipeline statistics counter IDs to MMIO addresses. */
const int *statistics_registers;
int entries_per_oa_snapshot;
} perfmon;
- int num_atoms;
- const struct brw_tracked_state **atoms;
+ int num_atoms[BRW_NUM_PIPELINES];
+ const struct brw_tracked_state render_atoms[57];
+ const struct brw_tracked_state compute_atoms[3];
/* If (INTEL_DEBUG & DEBUG_BATCH) */
struct {
uint32_t offset;
uint32_t size;
enum aub_state_struct_type type;
+ int index;
} *state_batch_list;
int state_batch_count;
struct {
drm_intel_bo *bo;
- struct gl_shader_program **shader_programs;
- struct gl_program **programs;
+ const char **names;
+ int *ids;
enum shader_time_shader_type *types;
- uint64_t *cumulative;
+ struct shader_times *cumulative;
int num_entries;
int max_entries;
double report_time;
struct intel_mipmap_tree *dst);
void brw_meta_fbo_stencil_blit(struct brw_context *brw,
+ struct gl_framebuffer *read_fb,
+ struct gl_framebuffer *draw_fb,
GLfloat srcX0, GLfloat srcY0,
GLfloat srcX1, GLfloat srcY1,
GLfloat dstX0, GLfloat dstY0,
void brw_store_register_mem64(struct brw_context *brw,
drm_intel_bo *bo, uint32_t reg, int idx);
+/** brw_conditional_render.c */
+void brw_init_conditional_render_functions(struct dd_function_table *functions);
+bool brw_check_conditional_render(struct brw_context *brw);
+
/** intel_batchbuffer.c */
void brw_load_register_mem(struct brw_context *brw,
uint32_t reg,
drm_intel_bo *bo,
uint32_t read_domains, uint32_t write_domain,
uint32_t offset);
+void brw_load_register_mem64(struct brw_context *brw,
+ uint32_t reg,
+ drm_intel_bo *bo,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t offset);
/*======================================================================
* brw_state_dump.c
/* brw_fs_reg_allocate.cpp
*/
-void brw_fs_alloc_reg_sets(struct intel_screen *screen);
+void brw_fs_alloc_reg_sets(struct brw_compiler *compiler);
/* brw_vec4_reg_allocate.cpp */
-void brw_vec4_alloc_reg_set(struct intel_screen *screen);
+void brw_vec4_alloc_reg_set(struct brw_compiler *compiler);
/* brw_disasm.c */
-int brw_disassemble_inst(FILE *file, struct brw_context *brw,
+int brw_disassemble_inst(FILE *file, const struct brw_device_info *devinfo,
struct brw_inst *inst, bool is_compacted);
/* brw_vs.c */
/* brw_draw_upload.c */
unsigned brw_get_vertex_surface_type(struct brw_context *brw,
const struct gl_client_array *glarray);
-unsigned brw_get_index_type(GLenum type);
+
+static inline unsigned
+brw_get_index_type(GLenum type)
+{
+ assert((type == GL_UNSIGNED_BYTE)
+ || (type == GL_UNSIGNED_SHORT)
+ || (type == GL_UNSIGNED_INT));
+
+ /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
+ * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
+ * to map to scale factors of 0, 1, and 2, respectively. These scale
+ * factors are then left-shfited by 8 to be in the correct position in the
+ * CMD_INDEX_BUFFER packet.
+ *
+ * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
+ * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
+ * the values the need to be written in the CMD_INDEX_BUFFER packet.
+ */
+ return (type - 0x1401) << 7;
+}
+
void brw_prepare_vertices(struct brw_context *brw);
/* brw_wm_surface_state.c */
void brw_upload_ubo_surfaces(struct brw_context *brw,
struct gl_shader *shader,
struct brw_stage_state *stage_state,
- struct brw_stage_prog_data *prog_data);
+ struct brw_stage_prog_data *prog_data,
+ bool dword_pitch);
void brw_upload_abo_surfaces(struct brw_context *brw,
struct gl_shader_program *prog,
struct brw_stage_state *stage_state,
struct brw_stage_prog_data *prog_data);
/* brw_surface_formats.c */
-bool brw_is_hiz_depth_format(struct brw_context *ctx, mesa_format format);
bool brw_render_target_supported(struct brw_context *brw,
struct gl_renderbuffer *rb);
uint32_t brw_depth_format(struct brw_context *brw, mesa_format format);
/* brw_blorp_blit.cpp */
GLbitfield
brw_blorp_framebuffer(struct brw_context *brw,
+ struct gl_framebuffer *readFb,
+ struct gl_framebuffer *drawFb,
GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
GLbitfield mask, GLenum filter);
extern GLenum
brw_get_graphics_reset_status(struct gl_context *ctx);
+/* brw_compute.c */
+extern void
+brw_init_compute_functions(struct dd_function_table *functions);
+
/*======================================================================
* Inline conversion functions. These are better-typed than the
* macros used previously:
return (const struct brw_fragment_program *) p;
}
+static inline struct brw_compute_program *
+brw_compute_program(struct gl_compute_program *p)
+{
+ return (struct brw_compute_program *) p;
+}
+
/**
* Pre-gen6, the register file of the EUs was shared between threads,
* and each thread used some subset allocated on a 16-register block
uint32_t get_hw_prim_for_gl_prim(int mode);
void
-brw_setup_vec4_key_clip_info(struct brw_context *brw,
- struct brw_vec4_prog_key *key,
- bool program_uses_clip_distance);
+brw_setup_vue_key_clip_info(struct brw_context *brw,
+ struct brw_vue_prog_key *key,
+ bool program_uses_clip_distance);
void
gen6_upload_push_constants(struct brw_context *brw,
struct brw_stage_state *stage_state,
enum aub_state_struct_type type);
-/* ================================================================
- * From linux kernel i386 header files, copes with odd sizes better
- * than COPY_DWORDS would:
- * XXX Put this in src/mesa/main/imports.h ???
- */
-#if defined(i386) || defined(__i386__)
-static inline void * __memcpy(void * to, const void * from, size_t n)
-{
- int d0, d1, d2;
- __asm__ __volatile__(
- "rep ; movsl\n\t"
- "testb $2,%b4\n\t"
- "je 1f\n\t"
- "movsw\n"
- "1:\ttestb $1,%b4\n\t"
- "je 2f\n\t"
- "movsb\n"
- "2:"
- : "=&c" (d0), "=&D" (d1), "=&S" (d2)
- :"0" (n/4), "q" (n),"1" ((long) to),"2" ((long) from)
- : "memory");
- return (to);
-}
-#else
-#define __memcpy(a,b,c) memcpy(a,b,c)
-#endif
+bool
+gen9_use_linear_1d_layout(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt);
+
+/* brw_pipe_control.c */
+int brw_init_pipe_control(struct brw_context *brw,
+ const struct brw_device_info *info);
+void brw_fini_pipe_control(struct brw_context *brw);
+
+void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags);
+void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
+ drm_intel_bo *bo, uint32_t offset,
+ uint32_t imm_lower, uint32_t imm_upper);
+void brw_emit_mi_flush(struct brw_context *brw);
+void brw_emit_post_sync_nonzero_flush(struct brw_context *brw);
+void brw_emit_depth_stall_flushes(struct brw_context *brw);
+void gen7_emit_vs_workaround_flush(struct brw_context *brw);
+void gen7_emit_cs_stall_flush(struct brw_context *brw);
#ifdef __cplusplus
}
projects / mesa.git / blobdiff