/*
Copyright (C) Intel Corp. 2006. All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
+ Intel funded Tungsten Graphics to
develop this 3D driver.
-
+
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
-
+
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
-
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
+
**********************************************************************/
/*
* Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
+ * Keith Whitwell <keithw@vmware.com>
*/
#include "main/mm.h"
#include "main/mtypes.h"
#include "brw_structs.h"
+#include "intel_aub.h"
+#include "program/prog_parameter.h"
#ifdef __cplusplus
extern "C" {
#include "intel_debug.h"
#include "intel_screen.h"
#include "intel_tex_obj.h"
+#include "intel_resolve_map.h"
/* Glossary:
*
*
* VUE - vertex URB entry. An urb entry holding a vertex and usually
* a vertex header. The header contains control information and
- * things like primitive type, Begin/end flags and clip codes.
+ * things like primitive type, Begin/end flags and clip codes.
*
* PUE - primitive URB entry. An urb entry produced by the setup (SF)
* unit holding rasterization and interpolation parameters.
* Handles blending and (presumably) depth and stencil testing.
*/
-#define INTEL_WRITE_PART 0x1
-#define INTEL_WRITE_FULL 0x2
-#define INTEL_READ 0x4
-
-#define BRW_MAX_CURBE (32*16)
-
struct brw_context;
-struct brw_instruction;
+struct brw_inst;
struct brw_vs_prog_key;
struct brw_vec4_prog_key;
struct brw_wm_prog_key;
BRW_STATE_META_IN_PROGRESS,
BRW_STATE_INTERPOLATION_MAP,
BRW_STATE_PUSH_CONSTANT_ALLOCATION,
+ BRW_STATE_NUM_SAMPLES,
BRW_NUM_STATE_BITS
};
#define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
#define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
#define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
+#define BRW_NEW_NUM_SAMPLES (1 << BRW_STATE_NUM_SAMPLES)
struct brw_state_flags {
/** State update flags signalled by mesa internals */
/**
* State update flags signalled as the result of brw_tracked_state updates
*/
- GLuint brw;
- /** State update flags signalled by brw_state_cache.c searches */
+ uint64_t brw;
+ /**
+ * State update flags that used to be signalled by brw_state_cache.c
+ * searches.
+ *
+ * Now almost all of that state is just streamed out on demand, but the
+ * flags for those state blobs updating have stayed in the same bitfield.
+ * brw_state_cache.c still flags CACHE_NEW_*_PROG.
+ */
GLuint cache;
};
-#define AUB_TRACE_TYPE_MASK 0x0000ff00
-#define AUB_TRACE_TYPE_NOTYPE (0 << 8)
-#define AUB_TRACE_TYPE_BATCH (1 << 8)
-#define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
-#define AUB_TRACE_TYPE_2D_MAP (6 << 8)
-#define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
-#define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
-#define AUB_TRACE_TYPE_1D_MAP (10 << 8)
-#define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
-#define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
-#define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
-#define AUB_TRACE_TYPE_GENERAL (14 << 8)
-#define AUB_TRACE_TYPE_SURFACE (15 << 8)
/**
- * state_struct_type enum values are encoded with the top 16 bits representing
- * the type to be delivered to the .aub file, and the bottom 16 bits
- * representing the subtype. This macro performs the encoding.
+ * Enum representing the different pipelines.
*/
-#define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
-
-enum state_struct_type {
- AUB_TRACE_VS_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 1),
- AUB_TRACE_GS_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 2),
- AUB_TRACE_CLIP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 3),
- AUB_TRACE_SF_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 4),
- AUB_TRACE_WM_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 5),
- AUB_TRACE_CC_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 6),
- AUB_TRACE_CLIP_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 7),
- AUB_TRACE_SF_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 8),
- AUB_TRACE_CC_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x9),
- AUB_TRACE_SAMPLER_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xa),
- AUB_TRACE_KERNEL_INSTRUCTIONS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xb),
- AUB_TRACE_SCRATCH_SPACE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xc),
- AUB_TRACE_SAMPLER_DEFAULT_COLOR = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xd),
-
- AUB_TRACE_SCISSOR_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x15),
- AUB_TRACE_BLEND_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x16),
- AUB_TRACE_DEPTH_STENCIL_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x17),
-
- AUB_TRACE_VERTEX_BUFFER = ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER, 0),
- AUB_TRACE_BINDING_TABLE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE, 0x100),
- AUB_TRACE_SURFACE_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE, 0x200),
- AUB_TRACE_VS_CONSTANTS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER, 0),
- AUB_TRACE_WM_CONSTANTS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER, 1),
-};
+typedef enum {
+ /**
+ * 3D rendering pipeline (vertex through fragment shader).
+ */
+ BRW_PIPELINE_3D,
+
+ /**
+ * Compute shader pipeline.
+ */
+ BRW_PIPELINE_COMPUTE,
+
+ BRW_NUM_PIPELINES
+} brw_pipeline;
+
/**
- * Decode a state_struct_type value to determine the type that should be
- * stored in the .aub file.
+ * Set one of the bits in a field of brw_state_flags.
*/
-static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type)
-{
- return (ss_type & 0xFFFF0000) >> 16;
-}
+#define SET_DIRTY_BIT(FIELD, FLAG) \
+ do { \
+ for (int pipeline = 0; pipeline < BRW_NUM_PIPELINES; pipeline++) \
+ brw->state.pipeline_dirty[pipeline].FIELD |= (FLAG); \
+ } while (false)
+
/**
- * Decode a state_struct_type value to determine the subtype that should be
- * stored in the .aub file.
+ * Set all of the bits in a field of brw_state_flags.
*/
-static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type)
-{
- return ss_type & 0xFFFF;
-}
+#define SET_DIRTY_ALL(FIELD) \
+ do { \
+ /* ~0 == 0xffffffff, so make sure field is <= 32 bits */ \
+ STATIC_ASSERT(sizeof(brw->state.pipeline_dirty[0].FIELD) == 4); \
+ for (int pipeline = 0; pipeline < BRW_NUM_PIPELINES; pipeline++) \
+ brw->state.pipeline_dirty[pipeline].FIELD = ~0; \
+ } while (false)
+
+
+/**
+ * Set all of the bits in a field of brw_state_flags.
+ */
+#define SET_DIRTY64_ALL(FIELD) \
+ do { \
+ /* ~0ULL == 0xffffffffffffffff, so make sure field is <= 64 bits */ \
+ STATIC_ASSERT(sizeof(brw->state.pipeline_dirty[0].FIELD) == 8); \
+ for (int pipeline = 0; pipeline < BRW_NUM_PIPELINES; pipeline++) \
+ brw->state.pipeline_dirty[pipeline].FIELD = ~(0ULL); \
+ } while (false)
+
+
+/**
+ * Check one of the bits in a field of brw_state_flags.
+ */
+#define CHECK_DIRTY_BIT(FIELD, FLAG) \
+ ((brw->state.pipeline_dirty[brw->state.current_pipeline].FIELD & (FLAG)) \
+ != 0)
+
/** Subclass of Mesa vertex program */
struct brw_vertex_program {
GLuint id; /**< serial no. to identify frag progs, never re-used */
};
+
+/** Subclass of Mesa compute program */
+struct brw_compute_program {
+ struct gl_compute_program program;
+ unsigned id; /**< serial no. to identify compute progs, never re-used */
+};
+
+
struct brw_shader {
struct gl_shader base;
bool compiled_once;
-
- /** Shader IR transformed for native compile, at link time. */
- struct exec_list *ir;
};
/* Note: If adding fields that need anything besides a normal memcmp() for
- * comparing them, be sure to go fix the the stage-specific
- * prog_data_compare().
+ * comparing them, be sure to go fix brw_stage_prog_data_compare().
*/
struct brw_stage_prog_data {
struct {
uint32_t shader_time_start;
/** @} */
} binding_table;
+
+ GLuint nr_params; /**< number of float params/constants */
+ GLuint nr_pull_params;
+
+ unsigned curb_read_length;
+ unsigned total_scratch;
+
+ /**
+ * Register where the thread expects to find input data from the URB
+ * (typically uniforms, followed by vertex or fragment attributes).
+ */
+ unsigned dispatch_grf_start_reg;
+
+ /* Pointers to tracked values (only valid once
+ * _mesa_load_state_parameters has been called at runtime).
+ *
+ * These must be the last fields of the struct (see
+ * brw_stage_prog_data_compare()).
+ */
+ const gl_constant_value **param;
+ const gl_constant_value **pull_param;
};
/* Data about a particular attempt to compile a program. Note that
struct brw_wm_prog_data {
struct brw_stage_prog_data base;
- GLuint curb_read_length;
GLuint num_varying_inputs;
- GLuint first_curbe_grf;
- GLuint first_curbe_grf_16;
+ GLuint dispatch_grf_start_reg_16;
GLuint reg_blocks;
GLuint reg_blocks_16;
- GLuint total_scratch;
struct {
/** @{
/** @} */
} binding_table;
- GLuint nr_params; /**< number of float params/constants */
- GLuint nr_pull_params;
+ bool no_8;
bool dual_src_blend;
bool uses_pos_offset;
bool uses_omask;
* For varying slots that are not used by the FS, the value is -1.
*/
int urb_setup[VARYING_SLOT_MAX];
-
- /* Pointers to tracked values (only valid once
- * _mesa_load_state_parameters has been called at runtime).
- *
- * These must be the last fields of the struct (see
- * brw_wm_prog_data_compare()).
- */
- const float **param;
- const float **pull_param;
};
/**
struct brw_stage_prog_data base;
struct brw_vue_map vue_map;
- /**
- * Register where the thread expects to find input data from the URB
- * (typically uniforms, followed by per-vertex inputs).
- */
- unsigned dispatch_grf_start_reg;
-
- GLuint curb_read_length;
GLuint urb_read_length;
GLuint total_grf;
- GLuint nr_params; /**< number of float params/constants */
- GLuint nr_pull_params; /**< number of dwords referenced by pull_param[] */
- GLuint total_scratch;
/* Used for calculating urb partitions. In the VS, this is the size of the
* URB entry used for both input and output to the thread. In the GS, this
* is the size of the URB entry used for output.
*/
GLuint urb_entry_size;
-
- /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
- const float **param;
- const float **pull_param;
};
bool include_primitive_id;
+ int invocations;
+
/**
* True if the thread should be dispatched in DUAL_INSTANCE mode, false if
* it should be dispatched in DUAL_OBJECT mode.
};
/** Number of texture sampler units */
-#define BRW_MAX_TEX_UNIT 16
+#define BRW_MAX_TEX_UNIT 32
/** Max number of render targets in a shader */
#define BRW_MAX_DRAW_BUFFERS 8
/** Max number of atomic counter buffer objects in a shader */
-#define BRW_MAX_ABO 4
+#define BRW_MAX_ABO 16
/**
* Max number of binding table entries used for stream output.
uint32_t size;
struct brw_cache_item *next;
-};
+};
typedef bool (*cache_aux_compare_func)(const void *a, const void *b);
ST_VS,
ST_VS_WRITTEN,
ST_VS_RESET,
+ ST_GS,
+ ST_GS_WRITTEN,
+ ST_GS_RESET,
ST_FS8,
ST_FS8_WRITTEN,
ST_FS8_RESET,
#define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
#define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
-struct brw_cached_batch_item {
- struct header *header;
- GLuint sz;
- struct brw_cached_batch_item *next;
-};
-
struct brw_vertex_buffer {
/** Buffer object containing the uploaded vertex data */
drm_intel_bo *bo;
int buffer;
- /** The corresponding Mesa vertex attribute */
- gl_vert_attrib attrib;
/** Offset of the first element within the buffer object */
unsigned int offset;
};
drm_intel_bo *bo;
};
+enum brw_gpu_ring {
+ UNKNOWN_RING,
+ RENDER_RING,
+ BLT_RING,
+};
+
struct intel_batchbuffer {
/** Current batchbuffer being queued up. */
drm_intel_bo *bo;
drm_intel_bo *workaround_bo;
bool need_workaround_flush;
- struct cached_batch_item *cached_items;
-
uint16_t emit, total;
uint16_t used, reserved_space;
uint32_t *map;
#define BATCH_SZ (8192*sizeof(uint32_t))
uint32_t state_batch_offset;
- bool is_blit;
+ enum brw_gpu_ring ring;
bool needs_sol_reset;
struct {
/** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
drm_intel_bo *offset_bo;
+ /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
+ bool zero_offsets;
+
/** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
GLenum primitive_mode;
*/
struct brw_stage_state
{
+ gl_shader_stage stage;
struct brw_stage_prog_data *prog_data;
/**
*/
drm_intel_bo *scratch_bo;
- /** Pull constant buffer */
- drm_intel_bo *const_bo;
-
/** Offset in the program cache to the program */
uint32_t prog_offset;
/** SAMPLER_STATE count and table offset */
uint32_t sampler_count;
uint32_t sampler_offset;
-
- /** Offsets in the batch to sampler default colors (texture border color) */
- uint32_t sdc_offset[BRW_MAX_TEX_UNIT];
};
/**
* brw_context is derived from gl_context.
*/
-struct brw_context
+struct brw_context
{
struct gl_context ctx; /**< base class, must be first field */
unsigned mocs,
bool rw);
- /** Upload a SAMPLER_STATE table. */
- void (*upload_sampler_state_table)(struct brw_context *brw,
- struct gl_program *prog,
- uint32_t sampler_count,
- uint32_t *sst_offset,
- uint32_t *sdc_offset);
-
/**
* Send the appropriate state packets to configure depth, stencil, and
* HiZ buffers (i965+ only)
drm_intel_context *hw_ctx;
+ /**
+ * Set of drm_intel_bo * that have been rendered to within this batchbuffer
+ * and would need flushing before being used from another cache domain that
+ * isn't coherent with it (i.e. the sampler).
+ */
+ struct set *render_cache;
+
/**
* Number of resets observed in the system at context creation.
*
struct {
drm_intel_bo *bo;
- GLuint offset;
- uint32_t buffer_len;
- uint32_t buffer_offset;
- char buffer[4096];
+ uint32_t next_offset;
} upload;
/**
*/
bool front_buffer_dirty;
- /**
- * Track whether front-buffer rendering is currently enabled
- *
- * A separate flag is used to track this in order to support MRT more
- * easily.
- */
- bool is_front_buffer_rendering;
-
- /**
- * Track whether front-buffer is the current read target.
- *
- * This is closely associated with is_front_buffer_rendering, but may
- * be set separately. The DRI2 fake front buffer must be referenced
- * either way.
- */
- bool is_front_buffer_reading;
-
/** Framerate throttling: @{ */
drm_intel_bo *first_post_swapbuffers_batch;
bool need_throttle;
bool is_g4x;
bool is_baytrail;
bool is_haswell;
+ bool is_cherryview;
bool has_hiz;
bool has_separate_stencil;
bool has_compr4;
bool has_negative_rhw_bug;
bool has_pln;
+ bool no_simd8;
+ bool use_rep_send;
/**
* Some versions of Gen hardware don't do centroid interpolation correctly
GLuint NewGLState;
struct {
- struct brw_state_flags dirty;
+ struct brw_state_flags pipeline_dirty[BRW_NUM_PIPELINES];
+ brw_pipeline current_pipeline;
} state;
struct brw_cache cache;
- struct brw_cached_batch_item *cached_batch_items;
+
+ /** IDs for meta stencil blit shader programs. */
+ unsigned meta_stencil_blit_programs[2];
/* Whether a meta-operation is in progress. */
bool meta_in_progress;
+ /* Whether the last depth/stencil packets were both NULL. */
+ bool no_depth_or_stencil;
+
struct {
struct brw_vertex_element inputs[VERT_ATTRIB_MAX];
struct brw_vertex_buffer buffers[VERT_ATTRIB_MAX];
unsigned int start_vertex_offset;
} ib;
- /* Active vertex program:
+ /* Active vertex program:
*/
const struct gl_vertex_program *vertex_program;
const struct gl_geometry_program *geometry_program;
const struct gl_fragment_program *fragment_program;
- /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
- uint32_t CMD_VF_STATISTICS;
- /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
- uint32_t CMD_PIPELINE_SELECT;
+ /**
+ * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
+ * that we don't have to reemit that state every time we change FBOs.
+ */
+ int num_samples;
/**
* Platform specific constants containing the maximum number of threads
bool gen6_gs_previously_active;
} urb;
-
- /* BRW_NEW_CURBE_OFFSETS:
+
+ /* BRW_NEW_CURBE_OFFSETS:
*/
struct {
GLuint wm_start; /**< pos of first wm const in CURBE buffer */
GLuint vs_size;
GLuint total_size;
+ /**
+ * Pointer to the (intel_upload.c-generated) BO containing the uniforms
+ * for upload to the CURBE.
+ */
drm_intel_bo *curbe_bo;
/** Offset within curbe_bo of space for current curbe entry */
GLuint curbe_offset;
- /** Offset within curbe_bo of space for next curbe entry */
- GLuint curbe_next_offset;
-
- /**
- * Copy of the last set of CURBEs uploaded. Frequently we'll end up
- * in brw_curbe.c with the same set of constant data to be uploaded,
- * so we'd rather not upload new constants in that case (it can cause
- * a pipeline bubble since only up to 4 can be pipelined at a time).
- */
- GLfloat *last_buf;
- /**
- * Allocation for where to calculate the next set of CURBEs.
- * It's a hot enough path that malloc/free of that data matters.
- */
- GLfloat *next_buf;
- GLuint last_bufsz;
} curbe;
/**
*/
struct brw_vue_map vue_map_geom_out;
- /**
- * Data structures used by all vec4 program compiles (not specific to any
- * particular program).
- */
- struct {
- struct ra_regs *regs;
-
- /**
- * Array of the ra classes for the unaligned contiguous register
- * block sizes used.
- */
- int *classes;
-
- /**
- * Mapping for register-allocated objects in *regs to the first
- * GRF for that object.
- */
- uint8_t *ra_reg_to_grf;
- } vec4;
-
struct {
struct brw_stage_state base;
struct brw_vs_prog_data *prog_data;
struct {
struct brw_stage_state base;
struct brw_gs_prog_data *prog_data;
+
+ /**
+ * True if the 3DSTATE_GS command most recently emitted to the 3D
+ * pipeline enabled the GS; false otherwise.
+ */
+ bool enabled;
} gs;
struct {
uint32_t prog_offset;
uint32_t state_offset;
uint32_t vp_offset;
+ bool viewport_transform_enable;
} sf;
struct {
* Gen6. See brw_update_null_renderbuffer_surface().
*/
drm_intel_bo *multisampled_null_render_target_bo;
-
- struct {
- struct ra_regs *regs;
-
- /**
- * Array of the ra classes for the unaligned contiguous register
- * block sizes used, indexed by register size.
- */
- int classes[16];
-
- /**
- * Mapping for register-allocated objects in *regs to the first
- * GRF for that object.
- */
- uint8_t *ra_reg_to_grf;
-
- /**
- * ra class for the aligned pairs we use for PLN, which doesn't
- * appear in *classes.
- */
- int aligned_pairs_class;
- } reg_sets[2];
+ uint32_t fast_clear_op;
} wm;
bool begin_emitted;
} query;
- int num_atoms;
- const struct brw_tracked_state **atoms;
+ struct {
+ /** A map from pipeline statistics counter IDs to MMIO addresses. */
+ const int *statistics_registers;
+
+ /** The number of active monitors using OA counters. */
+ unsigned oa_users;
+
+ /**
+ * A buffer object storing OA counter snapshots taken at the start and
+ * end of each batch (creating "bookends" around the batch).
+ */
+ drm_intel_bo *bookend_bo;
+
+ /** The number of snapshots written to bookend_bo. */
+ int bookend_snapshots;
+
+ /**
+ * An array of monitors whose results haven't yet been assembled based on
+ * the data in buffer objects.
+ *
+ * These may be active, or have already ended. However, the results
+ * have not been requested.
+ */
+ struct brw_perf_monitor_object **unresolved;
+ int unresolved_elements;
+ int unresolved_array_size;
+
+ /**
+ * Mapping from a uint32_t offset within an OA snapshot to the ID of
+ * the counter which MI_REPORT_PERF_COUNT stores there.
+ */
+ const int *oa_snapshot_layout;
+
+ /** Number of 32-bit entries in a hardware counter snapshot. */
+ int entries_per_oa_snapshot;
+ } perfmon;
+
+ int num_atoms[BRW_NUM_PIPELINES];
+ const struct brw_tracked_state **atoms[BRW_NUM_PIPELINES];
/* If (INTEL_DEBUG & DEBUG_BATCH) */
struct {
uint32_t offset;
uint32_t size;
- enum state_struct_type type;
+ enum aub_state_struct_type type;
} *state_batch_list;
int state_batch_count;
double report_time;
} shader_time;
+ struct brw_fast_clear_state *fast_clear_state;
+
__DRIcontext *driContext;
struct intel_screen *intelScreen;
};
-static INLINE bool
-is_power_of_two(uint32_t value)
-{
- return (value & (value - 1)) == 0;
-}
-
/*======================================================================
* brw_vtbl.c
*/
/*======================================================================
* brw_context.c
*/
-extern void intelFinish(struct gl_context * ctx);
+extern const char *const brw_vendor_string;
+
+extern const char *brw_get_renderer_string(unsigned deviceID);
enum {
DRI_CONF_BO_REUSE_DISABLED,
unsigned *error,
void *sharedContextPrivate);
+/*======================================================================
+ * brw_misc_state.c
+ */
+GLuint brw_get_rb_for_slice(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ unsigned level, unsigned layer, bool flat);
+
+void brw_meta_updownsample(struct brw_context *brw,
+ struct intel_mipmap_tree *src,
+ struct intel_mipmap_tree *dst);
+
+void brw_meta_fbo_stencil_blit(struct brw_context *brw,
+ GLfloat srcX0, GLfloat srcY0,
+ GLfloat srcX1, GLfloat srcY1,
+ GLfloat dstX0, GLfloat dstY0,
+ GLfloat dstX1, GLfloat dstY1);
+
+void brw_meta_stencil_updownsample(struct brw_context *brw,
+ struct intel_mipmap_tree *src,
+ struct intel_mipmap_tree *dst);
+
+bool brw_meta_fast_clear(struct brw_context *brw,
+ struct gl_framebuffer *fb,
+ GLbitfield mask,
+ bool partial_clear);
+
+void
+brw_meta_resolve_color(struct brw_context *brw,
+ struct intel_mipmap_tree *mt);
+void
+brw_meta_fast_clear_free(struct brw_context *brw);
+
+
/*======================================================================
* brw_misc_state.c
*/
/** gen6_queryobj.c */
void gen6_init_queryobj_functions(struct dd_function_table *functions);
+void brw_write_timestamp(struct brw_context *brw, drm_intel_bo *bo, int idx);
+void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *bo, int idx);
void brw_store_register_mem64(struct brw_context *brw,
drm_intel_bo *bo, uint32_t reg, int idx);
+/** intel_batchbuffer.c */
+void brw_load_register_mem(struct brw_context *brw,
+ uint32_t reg,
+ drm_intel_bo *bo,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t offset);
+
/*======================================================================
* brw_state_dump.c
*/
/* brw_fs_reg_allocate.cpp
*/
-void brw_fs_alloc_reg_sets(struct brw_context *brw);
+void brw_fs_alloc_reg_sets(struct intel_screen *screen);
/* brw_vec4_reg_allocate.cpp */
-void brw_vec4_alloc_reg_set(struct brw_context *brw);
+void brw_vec4_alloc_reg_set(struct intel_screen *screen);
/* brw_disasm.c */
-int brw_disasm (FILE *file, struct brw_instruction *inst, int gen);
+int brw_disassemble_inst(FILE *file, struct brw_context *brw,
+ struct brw_inst *inst, bool is_compacted);
/* brw_vs.c */
gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
unsigned brw_get_vertex_surface_type(struct brw_context *brw,
const struct gl_client_array *glarray);
unsigned brw_get_index_type(GLenum type);
+void brw_prepare_vertices(struct brw_context *brw);
/* brw_wm_surface_state.c */
void brw_init_surface_formats(struct brw_context *brw);
struct brw_stage_prog_data *prog_data);
/* brw_surface_formats.c */
-bool brw_is_hiz_depth_format(struct brw_context *ctx, gl_format format);
+bool brw_is_hiz_depth_format(struct brw_context *ctx, mesa_format format);
bool brw_render_target_supported(struct brw_context *brw,
struct gl_renderbuffer *rb);
+uint32_t brw_depth_format(struct brw_context *brw, mesa_format format);
+
+/* brw_performance_monitor.c */
+void brw_init_performance_monitors(struct brw_context *brw);
+void brw_dump_perf_monitors(struct brw_context *brw);
+void brw_perf_monitor_new_batch(struct brw_context *brw);
+void brw_perf_monitor_finish_batch(struct brw_context *brw);
+
+/* intel_buffer_objects.c */
+int brw_bo_map(struct brw_context *brw, drm_intel_bo *bo, int write_enable,
+ const char *bo_name);
+int brw_bo_map_gtt(struct brw_context *brw, drm_intel_bo *bo,
+ const char *bo_name);
/* intel_extensions.c */
extern void intelInitExtensions(struct gl_context *ctx);
int width, int height);
/* gen6_multisample_state.c */
+unsigned
+gen6_determine_sample_mask(struct brw_context *brw);
+
void
gen6_emit_3dstate_multisample(struct brw_context *brw,
unsigned num_samples);
void
-gen6_emit_3dstate_sample_mask(struct brw_context *brw,
- unsigned num_samples, float coverage,
- bool coverage_invert, unsigned sample_mask);
+gen6_emit_3dstate_sample_mask(struct brw_context *brw, unsigned mask);
void
gen6_get_sample_position(struct gl_context *ctx,
struct gl_framebuffer *fb,
GLuint index,
GLfloat *result);
+/* gen8_multisample_state.c */
+void gen8_emit_3dstate_multisample(struct brw_context *brw, unsigned num_samp);
+void gen8_emit_3dstate_sample_pattern(struct brw_context *brw);
+
/* gen7_urb.c */
void
gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
* Inline conversion functions. These are better-typed than the
* macros used previously:
*/
-static INLINE struct brw_context *
+static inline struct brw_context *
brw_context( struct gl_context *ctx )
{
return (struct brw_context *)ctx;
}
-static INLINE struct brw_vertex_program *
+static inline struct brw_vertex_program *
brw_vertex_program(struct gl_vertex_program *p)
{
return (struct brw_vertex_program *) p;
}
-static INLINE const struct brw_vertex_program *
+static inline const struct brw_vertex_program *
brw_vertex_program_const(const struct gl_vertex_program *p)
{
return (const struct brw_vertex_program *) p;
}
-static INLINE struct brw_geometry_program *
+static inline struct brw_geometry_program *
brw_geometry_program(struct gl_geometry_program *p)
{
return (struct brw_geometry_program *) p;
}
-static INLINE struct brw_fragment_program *
+static inline struct brw_fragment_program *
brw_fragment_program(struct gl_fragment_program *p)
{
return (struct brw_fragment_program *) p;
}
-static INLINE const struct brw_fragment_program *
+static inline const struct brw_fragment_program *
brw_fragment_program_const(const struct gl_fragment_program *p)
{
return (const struct brw_fragment_program *) p;
prog_offset,
I915_GEM_DOMAIN_INSTRUCTION, 0);
- return brw->cache.bo->offset + prog_offset;
+ return brw->cache.bo->offset64 + prog_offset;
}
bool brw_do_cubemap_normalize(struct exec_list *instructions);
bool brw_lower_texture_gradients(struct brw_context *brw,
struct exec_list *instructions);
-bool brw_do_lower_offset_arrays(struct exec_list *instructions);
bool brw_do_lower_unnormalized_offset(struct exec_list *instructions);
struct opcode_desc {
};
extern const struct opcode_desc opcode_descs[128];
+extern const char * const conditional_modifier[16];
void
brw_emit_depthbuffer(struct brw_context *brw);
uint32_t width, uint32_t height,
uint32_t tile_x, uint32_t tile_y);
+void
+gen6_emit_depth_stencil_hiz(struct brw_context *brw,
+ struct intel_mipmap_tree *depth_mt,
+ uint32_t depth_offset, uint32_t depthbuffer_format,
+ uint32_t depth_surface_type,
+ struct intel_mipmap_tree *stencil_mt,
+ bool hiz, bool separate_stencil,
+ uint32_t width, uint32_t height,
+ uint32_t tile_x, uint32_t tile_y);
+
void
gen7_emit_depth_stencil_hiz(struct brw_context *brw,
struct intel_mipmap_tree *depth_mt,
bool hiz, bool separate_stencil,
uint32_t width, uint32_t height,
uint32_t tile_x, uint32_t tile_y);
+void
+gen8_emit_depth_stencil_hiz(struct brw_context *brw,
+ struct intel_mipmap_tree *depth_mt,
+ uint32_t depth_offset, uint32_t depthbuffer_format,
+ uint32_t depth_surface_type,
+ struct intel_mipmap_tree *stencil_mt,
+ bool hiz, bool separate_stencil,
+ uint32_t width, uint32_t height,
+ uint32_t tile_x, uint32_t tile_y);
+
+void gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
+ unsigned int level, unsigned int layer, enum gen6_hiz_op op);
-extern const GLuint prim_to_hw_prim[GL_TRIANGLE_STRIP_ADJACENCY+1];
+uint32_t get_hw_prim_for_gl_prim(int mode);
void
brw_setup_vec4_key_clip_info(struct brw_context *brw,
bool program_uses_clip_distance);
void
-gen6_upload_vec4_push_constants(struct brw_context *brw,
- const struct gl_program *prog,
- const struct brw_vec4_prog_data *prog_data,
- struct brw_stage_state *stage_state,
- enum state_struct_type type);
+gen6_upload_push_constants(struct brw_context *brw,
+ const struct gl_program *prog,
+ const struct brw_stage_prog_data *prog_data,
+ struct brw_stage_state *stage_state,
+ enum aub_state_struct_type type);
/* ================================================================
* From linux kernel i386 header files, copes with odd sizes better
* XXX Put this in src/mesa/main/imports.h ???
*/
#if defined(i386) || defined(__i386__)
-static INLINE void * __memcpy(void * to, const void * from, size_t n)
+static inline void * __memcpy(void * to, const void * from, size_t n)
{
int d0, d1, d2;
__asm__ __volatile__(
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