enum brw_state_id {
BRW_STATE_URB_FENCE,
BRW_STATE_FRAGMENT_PROGRAM,
+ BRW_STATE_GEOMETRY_PROGRAM,
BRW_STATE_VERTEX_PROGRAM,
BRW_STATE_CURBE_OFFSETS,
BRW_STATE_REDUCED_PRIMITIVE,
BRW_STATE_STATS_WM,
BRW_STATE_UNIFORM_BUFFER,
BRW_STATE_META_IN_PROGRESS,
+ BRW_STATE_INTERPOLATION_MAP,
+ BRW_NUM_STATE_BITS
};
#define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
#define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
+#define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
#define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
#define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
#define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
#define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
#define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
#define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
+#define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
struct brw_state_flags {
/** State update flags signalled by mesa internals */
};
+/** Subclass of Mesa geometry program */
+struct brw_geometry_program {
+ struct gl_geometry_program program;
+ unsigned id; /**< serial no. to identify geom progs, never re-used */
+};
+
+
/** Subclass of Mesa fragment program */
struct brw_fragment_program {
struct gl_fragment_program program;
GLuint reg_blocks_16;
GLuint total_scratch;
+ unsigned binding_table_size;
+
GLuint nr_params; /**< number of float params/constants */
GLuint nr_pull_params;
bool dual_src_blend;
GLbitfield64 slots_valid, bool userclip_active);
+/*
+ * Mapping of VUE map slots to interpolation modes.
+ */
+struct interpolation_mode_map {
+ unsigned char mode[BRW_VARYING_SLOT_COUNT];
+};
+
+static inline bool brw_any_flat_varyings(struct interpolation_mode_map *map)
+{
+ for (int i = 0; i < BRW_VARYING_SLOT_COUNT; i++)
+ if (map->mode[i] == INTERP_QUALIFIER_FLAT)
+ return true;
+
+ return false;
+}
+
+static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map *map)
+{
+ for (int i = 0; i < BRW_VARYING_SLOT_COUNT; i++)
+ if (map->mode[i] == INTERP_QUALIFIER_NOPERSPECTIVE)
+ return true;
+
+ return false;
+}
+
+
struct brw_sf_prog_data {
GLuint urb_read_length;
GLuint total_grf;
struct brw_vec4_prog_data {
struct brw_vue_map vue_map;
+ /**
+ * Register where the thread expects to find input data from the URB
+ * (typically uniforms, followed by per-vertex inputs).
+ */
+ unsigned dispatch_grf_start_reg;
+
GLuint curb_read_length;
GLuint urb_read_length;
GLuint total_grf;
*/
GLuint urb_entry_size;
- int num_surfaces;
+ unsigned binding_table_size;
/* These pointers must appear last. See brw_vec4_prog_data_compare(). */
const float **param;
bool uses_vertexid;
};
+
+/* Note: brw_vec4_gs_prog_data_compare() must be updated when adding fields to
+ * this struct!
+ */
+struct brw_vec4_gs_prog_data
+{
+ struct brw_vec4_prog_data base;
+
+ /**
+ * Size of an output vertex, measured in HWORDS (32 bytes).
+ */
+ unsigned output_vertex_size_hwords;
+
+ unsigned output_topology;
+};
+
/** Number of texture sampler units */
#define BRW_MAX_TEX_UNIT 16
* | : | : |
* | 63 | SOL Binding 63 |
* +-----+-------------------------+
- *
- * Note that nothing actually uses the SURF_INDEX_DRAW macro, so it has to be
- * the identity function or things will break. We do want to keep draw buffers
- * first so we can use headerless render target writes for RT 0.
*/
#define SURF_INDEX_DRAW(d) (d)
#define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
/**
- * brw_context is derived from intel_context.
+ * brw_context is derived from gl_context.
*/
struct brw_context
{
- struct intel_context intel; /**< base class, must be first field */
+ struct gl_context ctx; /**< base class, must be first field */
struct
{
uint32_t *out_offset,
bool dword_pitch);
+ /** Upload a SAMPLER_STATE table. */
+ void (*upload_sampler_state_table)(struct brw_context *brw,
+ struct gl_program *prog,
+ uint32_t sampler_count,
+ uint32_t *sst_offset,
+ uint32_t *sdc_offset);
+
/**
* Send the appropriate state packets to configure depth, stencil, and
* HiZ buffers (i965+ only)
struct intel_batchbuffer batch;
bool no_batch_wrap;
+ struct {
+ drm_intel_bo *bo;
+ GLuint offset;
+ uint32_t buffer_len;
+ uint32_t buffer_offset;
+ char buffer[4096];
+ } upload;
+
/**
* Set if rendering has occured to the drawable's front buffer.
*
uint32_t max_gtt_map_object_size;
bool emit_state_always;
+
+ int gen;
+ int gt;
+
+ bool is_g4x;
+ bool is_baytrail;
+ bool is_haswell;
+
+ bool has_hiz;
+ bool has_separate_stencil;
+ bool must_use_separate_stencil;
+ bool has_llc;
+ bool has_swizzling;
bool has_surface_tile_offset;
bool has_compr4;
bool has_negative_rhw_bug;
*/
bool needs_unlit_centroid_workaround;
+ GLuint NewGLState;
struct {
struct brw_state_flags dirty;
} state;
/* Active vertex program:
*/
const struct gl_vertex_program *vertex_program;
+ const struct gl_geometry_program *geometry_program;
const struct gl_fragment_program *fragment_program;
/* hw-dependent 3DSTATE_VF_STATISTICS opcode */
GLuint last_bufsz;
} curbe;
- /** SAMPLER_STATE count and offset */
- struct {
- GLuint count;
- uint32_t offset;
- } sampler;
-
/**
* Layout of vertex data exiting the geometry portion of the pipleine.
* This comes from the geometry shader if one exists, otherwise from the
uint32_t bind_bo_offset;
uint32_t surf_offset[BRW_MAX_VS_SURFACES];
+
+ /** SAMPLER_STATE count and table offset */
+ uint32_t sampler_count;
+ uint32_t sampler_offset;
+
+ /** Offsets in the batch to sampler default colors (texture border color)
+ */
+ uint32_t sdc_offset[BRW_MAX_TEX_UNIT];
} vs;
struct {
struct {
struct brw_wm_prog_data *prog_data;
- /** offsets in the batch to sampler default colors (texture border color)
- */
- uint32_t sdc_offset[BRW_MAX_TEX_UNIT];
-
GLuint render_surf;
drm_intel_bo *scratch_bo;
uint32_t bind_bo_offset;
uint32_t surf_offset[BRW_MAX_WM_SURFACES];
+ /** SAMPLER_STATE count and table offset */
+ uint32_t sampler_count;
+ uint32_t sampler_offset;
+
+ /** Offsets in the batch to sampler default colors (texture border color)
+ */
+ uint32_t sdc_offset[BRW_MAX_TEX_UNIT];
+
struct {
struct ra_regs *regs;
uint32_t render_target_format[MESA_FORMAT_COUNT];
bool format_supported_as_render_target[MESA_FORMAT_COUNT];
+ /* Interpolation modes, one byte per vue slot.
+ * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
+ */
+ struct interpolation_mode_map interpolation_mode;
+
/* PrimitiveRestart */
struct {
bool in_progress;
int max_entries;
double report_time;
} shader_time;
+
+ __DRIcontext *driContext;
+ struct intel_screen *intelScreen;
+ void (*saved_viewport)(struct gl_context *ctx,
+ GLint x, GLint y, GLsizei width, GLsizei height);
};
/*======================================================================
void brw_workaround_depthstencil_alignment(struct brw_context *brw,
GLbitfield clear_mask);
+/* brw_object_purgeable.c */
+void brw_init_object_purgeable_functions(struct dd_function_table *functions);
+
/*======================================================================
* brw_queryobj.c
*/
/* brw_vs.c */
gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
+/* brw_draw_upload.c */
+unsigned brw_get_vertex_surface_type(struct brw_context *brw,
+ const struct gl_client_array *glarray);
+unsigned brw_get_index_type(GLenum type);
+
/* brw_wm_surface_state.c */
void brw_init_surface_formats(struct brw_context *brw);
void
brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
uint32_t prog_offset)
{
- struct intel_context *intel = &brw->intel;
-
- if (intel->gen >= 5) {
+ if (brw->gen >= 5) {
/* Using state base address. */
return prog_offset;
}
projects / mesa.git / blobdiff