BRW_STATE_BLORP,
BRW_STATE_VIEWPORT_COUNT,
BRW_STATE_CONSERVATIVE_RASTERIZATION,
+ BRW_STATE_DRAW_CALL,
BRW_NUM_STATE_BITS
};
#define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
#define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
#define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
+#define BRW_NEW_DRAW_CALL (1ull << BRW_STATE_DRAW_CALL)
struct brw_state_flags {
/** State update flags signalled by mesa internals */
/** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
uint32_t state_offset;
- uint32_t push_const_offset; /* Offset in the batchbuffer */
+ struct brw_bo *push_const_bo; /* NULL if using the batchbuffer */
+ uint32_t push_const_offset; /* Offset in the push constant BO or batch */
int push_const_size; /* in 256-bit register increments */
/* Binding table: pointers to SURFACE_STATE entries. */
/** SAMPLER_STATE count and table offset */
uint32_t sampler_count;
uint32_t sampler_offset;
+
+ /** Need to re-emit 3DSTATE_CONSTANT_XS? */
+ bool push_constants_dirty;
};
enum brw_predicate_state {
/* In this case whether to draw or not depends on the result of an
* MI_PREDICATE command so the predicate enable bit needs to be checked.
*/
- BRW_PREDICATE_STATE_USE_BIT
+ BRW_PREDICATE_STATE_USE_BIT,
+ /* In this case, either MI_PREDICATE doesn't exist or we lack the
+ * necessary kernel features to use it. Stall for the query result.
+ */
+ BRW_PREDICATE_STATE_STALL_FOR_QUERY,
};
struct shader_times;
uint32_t width, uint32_t height,
uint32_t tile_x, uint32_t tile_y);
+ /**
+ * Emit an MI_REPORT_PERF_COUNT command packet.
+ *
+ * This asks the GPU to write a report of the current OA counter values
+ * into @bo at the given offset and containing the given @report_id
+ * which we can cross-reference when parsing the report (gen7+ only).
+ */
+ void (*emit_mi_report_perf_count)(struct brw_context *brw,
+ struct brw_bo *bo,
+ uint32_t offset_in_bytes,
+ uint32_t report_id);
} vtbl;
struct brw_bufmgr *bufmgr;
bool has_negative_rhw_bug;
bool has_pln;
bool no_simd8;
- bool use_rep_send;
/**
* Some versions of Gen hardware don't do centroid interpolation correctly
*/
bool needs_unlit_centroid_workaround;
+ /** Derived stencil states. */
+ bool stencil_enabled;
+ bool stencil_two_sided;
+ bool stencil_write_enabled;
+ /** Derived polygon state. */
+ bool polygon_front_bit; /**< 0=GL_CCW, 1=GL_CW */
+
struct isl_device isl_dev;
struct blorp_context blorp;
struct {
struct brw_stage_state base;
-
- /**
- * True if the 3DSTATE_HS command most recently emitted to the 3D
- * pipeline enabled the HS; false otherwise.
- */
- bool enabled;
} tcs;
struct {
struct brw_stage_state base;
-
- /**
- * True if the 3DSTATE_DS command most recently emitted to the 3D
- * pipeline enabled the DS; false otherwise.
- */
- bool enabled;
} tes;
struct {
uint64_t timestamp_frequency; /** $GpuTimestampFrequency */
uint64_t n_eus; /** $EuCoresTotalCount */
uint64_t n_eu_slices; /** $EuSlicesTotalCount */
+ uint64_t n_eu_sub_slices; /** $EuSubslicesTotalCount */
+ uint64_t eu_threads_count; /** $EuThreadsCount */
+ uint64_t slice_mask; /** $SliceMask */
uint64_t subslice_mask; /** $SubsliceMask */
uint64_t gt_min_freq; /** $GpuMinFrequency */
uint64_t gt_max_freq; /** $GpuMaxFrequency */
const struct brw_tracked_state render_atoms[76];
const struct brw_tracked_state compute_atoms[11];
- enum isl_format render_target_format[MESA_FORMAT_COUNT];
- bool format_supported_as_render_target[MESA_FORMAT_COUNT];
+ const enum isl_format *mesa_to_isl_render_format;
+ const bool *mesa_format_supports_render;
/* PrimitiveRestart */
struct {
* brw_workaround_depthstencil_alignment().
*/
struct {
- struct intel_mipmap_tree *depth_mt;
- struct intel_mipmap_tree *stencil_mt;
-
/* Inter-tile (page-aligned) byte offsets. */
- uint32_t depth_offset, hiz_offset, stencil_offset;
- /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
+ uint32_t depth_offset;
+ /* Intra-tile x,y offsets for drawing to combined depth-stencil. Only
+ * used for Gen < 6.
+ */
uint32_t tile_x, tile_y;
} depthstencil;
__DRIdrawable *drawable);
void intel_prepare_render(struct brw_context *brw);
+void brw_predraw_resolve_inputs(struct brw_context *brw);
+
void intel_resolve_for_dri2_flush(struct brw_context *brw,
__DRIdrawable *drawable);
struct brw_stage_prog_data *prog_data);
/* brw_surface_formats.c */
+void intel_screen_init_surface_formats(struct intel_screen *screen);
void brw_init_surface_formats(struct brw_context *brw);
bool brw_render_target_supported(struct brw_context *brw,
struct gl_renderbuffer *rb);
void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
struct brw_bo *bo, uint32_t offset,
uint64_t imm);
+void brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags);
void brw_emit_mi_flush(struct brw_context *brw);
void brw_emit_post_sync_nonzero_flush(struct brw_context *brw);
void brw_emit_depth_stall_flushes(struct brw_context *brw);
projects / mesa.git / blobdiff